CP3SP33SMSSLASHNOPB datasheet(19/407 Pages) TI1

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CP3SP33

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SNOSCW5 – MAY 2013

With the recommended calling convention for the architecture, some of these registers are assigned

special hardware and software functions. Registers R0 to R13 are for general-purpose use, such as

holding variables, addresses, or index values. The SP register holds a pointer to the program run-time

stack. The RA register holds a subroutine return address. The R12 and R13 registers are available to hold

base addresses used in the index addressing mode.

If a general-purpose register is specified by an operation that is 8 bits long, only the lower byte of the

pairs, only the lower word is used. The upper word is not referenced or modified.

5.2

Dedicated Address Registers

The CR16CPlus has four dedicated address registers to implement specific functions: the PC, ISP, USP,

and INTBASE registers.

5.2.1

Program Counter (PC) Register

The 24-bit value in the PC register points to the first byte of the instruction currently being executed.

CR16CPlus instructions are aligned to even addresses, therefore the least significant bit of the PC is

always 0. At reset, the PC is initialized to 0 or an optional predetermined value. When a warm reset

occurs, value of the PC prior to reset is saved in the (R1,R0) general-purpose register pair.

5.2.2

Interrupt Stack Pointer (ISP)

The 32-bit ISP register points to the top of the interrupt stack. This stack is used by hardware to service

exceptions (interrupts and traps). The stack pointer may be accessed as the ISP register for initialization.

The interrupt stack can be located anywhere in the CPU address space. The ISP cannot be used for any

purpose other than the interrupt stack, which is used for automatic storage of the CPU registers when an

exception occurs and restoration of these registers when the exception handler returns. The interrupt

stack grows downward in memory. The least significant bit and the 8 most significant bits of the ISP

5.2.3

User Stack Pointer (USP)

The USP register points to the top of the user-mode program stack. Separate stacks are available for user

and supervisor modes, to support protection mechanisms for multitasking software. The processor mode

is controlled by the U bit in the PSR register (which is called PSR.U in the shorthand convention). Stack

grow downward in memory. If the USP register points to an illegal address (any address greater than

0x00FF_FFFF) and the USP is used for stack access, an IAD trap is taken.

5.2.4

Interrupt Base Register (INTBASE)

The INTBASE register holds the address of the dispatch table for exceptions. The dispatch table can be

located any where in the CPU address space. When loading the INTBASE register, bits 31 to 24 and bit 0

must written with 0.

5.3

Processor Status Register (PSR)

Reserved

The Carry bit indicates whether a carry or borrow occurred after addition or subtraction.

0 – No carry or borrow occurred.

1 – Carry or borrow occurred.

The Trace bit enables execution tracing, in which a Trace trap (TRC) is taken after every instruction.

Tracing is automatically disabled during the execution of an exception handler.

0 – Tracing disabled.

1 – Tracing enabled.

CPU Architecture

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