CP3SP33SMSSLASHNOPB datasheet(35/407 Pages) TI1

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CP3SP33

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SNOSCW5 – MAY 2013

9.2.1

DSP Reset

There are two reset bits for the DSP:

•

ADMAC.DSPRSTN—this bit in the CPU/DSP interface asserts a reset signal that is external to the

DSP module.

•

PCFG.DSPR—this bit within the DSP module can be used to hold the DSP in reset.

The ADMAC.DSPRSTN bit is like a power-on reset, which should be used when complete reset of the

DSP is required. The DSP memories cannot be accessed while the ADMAC.DSPRSTN bit is clear (reset

asserted). The DSP clock (Auxiliary Clock 7) must be enabled for at least two cycles before the

ADMAC.DSPRSTN bit is set (reset deasserted). After deasserting reset, the PSTS.PRST bit can be polled

to determine when the DSP has completed its reset sequence.

The PCFG.DSPR bit can be used to hold the processor in reset while accessing the DSP block, for

example while downloading software to the DSP program memory. When asserted, it must be held for

eight DSP clock cycles before being deasserted.

9.2.2

Downloading to DSP Program Memory

The CPU interface can be used to download software to the DSP memories. After power-on-reset or other

system resets, the DSP will be held in reset with the DSP clock (Auxiliary Clock 7) enabled. The DSP

clock must be enabled during reset to properly reset the DSP.

1. Enable the clock to the DSP (if necessary).

2. Set the DSPR bit in the PCFG register. This will hold the DSP in reset.

3. Deassert the reset signal to the DSP module by setting the DSPRSTN bit in the ADMAC register. A

delay of at least two DSP clocks must be maintained between enabling the DSP clock and deasserting

the reset signal.

4. Poll the PRST bit in the PSTS register until a 1 to 0 transition is observed, which indicates that the

MMIO registers that control a DMA transfer have been reset.

5. Set up and perform the transfer.

6. Clear the DSPR bit in the PCFG register, which restarts the DSP.

9.2.3

Audio Subsystem Controller (ASC)

As shown in Figure 9-2, the ASC multiplexes the interrupt and DMA signals between the independent

interrupt and DMA controllers for the CPU and DSP. Peripherals capable of requesting interrupts from

both the CPU and DSP must have their selections programmed in the ASCINTSEL register, in addition to

having their requests enabled in the interrupt controllers. Peripherals capable of requesting DMA from

both the CPU and DSP must have their selections programmed in the ASCDMASELn registers, in addition

to having their requests enabled in the DMA controllers. By default after reset, all interrupt and DMA

requests are routed to the CPU interrupt and DMA controllers.

The DSP DMA controller provides eight DMA request inputs and eight DMA acknowledge outputs. For

each DSP DMA channel, a 5-bit field in the one of the ASCDDMASELn registers selects which of the 21

sources of DMA requests is serviced by that channel.

DSP and Audio Peripherals

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