CP3SP33SMSSLASHNOPB datasheet(64/407 Pages) TI1

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CP3SP33

SNOSCW5 – MAY 2013

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Device B Address Counter

12.9.4 Device B Address Register n (ADRBn)

The Device B Address register is a 32-bit, read/write register. It holds the starting address of either the

next source data block or the next destination data area, according to the DIR bit in the DMACNTn

Device B Address

12.9.5 Block Length Counter Register n (BLTCn)

The Block Length Counter register is a 32-bit, read/write register. It holds the current number of DMA

transfers to be executed in the current block. 0000 0000h is interpreted as 232-1 transfer cycles. BLTCn is

decremented by one after each transfer cycle. A DMA transfer may consist of 1, 2, or 4 bytes, as selected

by the TCS and WMODE bits in the DMACNTn register.

Block Length Counter

12.9.6 Block Length Register n (BLTRn)

The Block Length register is a 32-bit, read/write register. It holds the number of DMA transfers to be

performed for the next block. 0000 0000h is interpreted as 232-1 transfer cycles. Writing this register

automatically sets the DMASTAT.VLD bit.

Block Length

12.9.7 Request Timeout Register n (RQTRn)

The Request Timeout register is a 32-bit, read/write register. It holds the timeout time. After reset, the

RQTRn registers are clear.

15M M8

Reserved

Timeout

12.9.8 Request Timeout Counter Register n (RQTCNTn)

The Request Timeout Count register is a 32-bit, read-only register. It holds the current timeout count. A

RQTCNTn register is loaded from its corresponding RQTRn register when its DMA request is asserted.

The RQTCNTn register is decremented if the DMACNT.TOEN bit is set. After reset, the RQTCNTn

registers are clear.

15M M8

Reserved

Timeout Counter

12.9.9 DMA Control Register n (DMACNTn)

The DMA Control register is a 32-bit, read/write register that controls the operation of DMA channel n. This

CPU DMA Controller

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CP3SP33SMS/NOPB Datasheet(PDF) 64 Page - Texas Instruments