CP3SP33SMSSLASHNOPB datasheet(59/407 Pages) TI1

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CP3SP33

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SNOSCW5 – MAY 2013

12.3.1.2 Termination

When the DMAC is the flow controller, the transfer terminates when the transfer count in the BLTCn

On termination:

1. The DMASTAT.TC and DMASTAT.OVR bits are set, and the DMASTAT.CHAC bit is cleared.

2. An interrupt is asserted if enabled by the DMACNTn.ETC or DMACNTn.EOVR bits.

12.3.2 Double Buffer Mode

This mode allows software to set up the next DMA transfer while the current transfer proceeds.

12.3.2.1 Initialization

1. Select the peripheral device by writing the SRCRQ field in the DMACNTn register.

2. Write the block transfer addresses and byte count into the ADCAn, ADCBn, and BLTCn counters.

3. Clear the DMACNTn.OT bit to select non-auto-initialize mode. Clear the DMASTAT.VLD bit by writing

a 1 to it.

4. Set the DMACNTn.CHEN bit. This activates the cha nel and enables it to respond to DMA transfer

requests. If the DMACNTn register is loaded for any other reason, the DMACNTn.CHEN bit must be

clear to avoid prematurely starting a new DMA transfer.

5. While the current block transfer proceeds, write the addresses and byte count for the next block into

the ADRAn, ADRBn, and BLTRn registers. The BLTRn register must be written last, because writing

this register sets the DMASTAT.VLD bit which indicates to the DMAC that the parameters for the next

transfer have been updated.

12.3.2.2 Continuation/Termination

When the BLTCn counter reaches 0 (DMACNTn.PF = 0) or the last request has been processed

(DMACNTn.PF = 1):

1. If the DMACNTn.PF bit is clear, the DMASTATn.TC bit is set.

2. If enabled by the DMACNTn.ETC bit, an interrupt is asserted.

3. The DMAC channel checks the DMASTAT.VLD bit.

If the DMASTAT.VLD bit is set:

1. The channel copies the ADRAn, ADRBn, and BLTRn values into the ADCAn, ADCBn, and BLTCn

registers.

2. The DMASTAT.VLD bit is cleared.

3. The next block transfer is started.

If the DMASTAT.VLD bit is clear:

1. The transfer operation terminates.

2. The channel sets the DMASTAT.OVR bit.

3. The DMASTAT.CHAC bit is cleared.

4. If enabled by the DMACNTn.EOVR bit, an interrupt is asserted.

CPU DMA Controller

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