CP3SP33SMSSLASHNOPB datasheet(81/407 Pages) TI1

81 / 407 page

CP3SP33

www.ti.com

SNOSCW5 – MAY 2013

For systems that do not require a reduced power consumption mode, the external crystal network may be

omitted for the low-frequency oscillator. In this case, Slow Clock is synthesized by dividing the Main Clock

by a prescaler factor. The prescaler consists of a 14-bit prescaler. This allows a choice of clock divisors

ranging from 1 to 8192 in increments of 1/2 Main Clock period. The resulting Slow Clock frequency must

not exceed 100 kHz.

A software-controlled multiplexer selects either the prescaled Main Clock or the 32.768 kHz oscillator as

the Slow Clock. At reset, the prescaled Main Clock is selected, ensuring that the Slow Clock is always

present initially. Selection of the 32.768 kHz oscillator as the Slow Clock source disables the clock

prescaler, and it may allow the high-frequency oscillator to be turned off in some low-power modes, for

minimum power consumption and radiated emissions. The high-frequency oscillator cannot be disabled

when the prescaler is selected as the source for Slow Clock.

An external clock may be driven on the X2CKI input. It must not exceed 1.8V.

14.4 PLL Clocks

The CP3SP33 has two identical PLLs for generating clocks. These are two purposes for providing PLL

clock generators:

•

Higher Frequency—the PLLs can generate clock frequencies up to 96 MHz using the 12 MHz Main

Clock as a reference. Frequencies above 12 MHz are needed to run the CPU and DSP at their

maximum speed. Also, the USB peripheral requires a 60 MHz clock.

•

Synchronization with External Devices—some devices (such as external codecs) require operation at a

precise frequency which is not an integer multiple of a standard CP3SP33 clock frequency. By

synchronizing a PLL with the external device, it can be interfaced directly without treating its I/O as

asynchronous signals.

After reset, the PLLs are powered down. Software can program and enable the PLLs to start them

running. Each PLL has a programmable start-up counter to indicate when the PLL has become stable. By

default, the start-up counter will indicate the PLL has become stable after 32K cycles of the PLL Clock.

To enable the PLL after reset or after PLL power down, perform the following sequence:

1. Set the divider ratios in the PMMPLLnMDIV, PMMPLLnNDIV, PMMPLLnNMOD, and PMMPLLnPDIV

registers to acceptable values for the desired output frequency. If the number of PLL cycles to allow for

stabilization should be different from the default value (32K cycles), set the PLL Startup Counter

2. Power up the PLL by setting the PMMPLLnCTL1.PLLEN field to 01b.

3. Wait until the PMMPLLnCTL2.PLLCLKSTB bit has become set, which indicates the PLL is stable.

4. The PMMCKCTL.FCLKSRC field can then be loaded with 00b to select PLL1 Clock as the source for

the HCLK Clock. It can be loaded with 01b to select PLL2 Clock as the source. The switch only occurs

if the selected PLL is stable. To switch from PLL1 Clock to PLL2 Clock, Main Clock must be selected

as the clock source during an intermediate step (direct switching between the two PLL Clocks is not

allowed).

If any of the divisors (PMMPLLnMDIV, PMMPLLnNDIV, PMMPLLnNMOD, and PMMPLLnPDIV) are to

be changed, the HCLK Clock source must be switched to Main Clock (if the PLL was driving HCLK

Clock), and the PLL must be powered down (for example, by clearing the PMMPLLnCTL1.PLLEN

field). Then, the procedure above may be performed to restart the PLL after loading new values in the

registers.

14.4.1 PLL Programming

The

PLLs

have

the

structure

shown

Figure

14-4.

The

PMMPLLnMDIV,

PMMPLLnNDIV,

PMMPLLnNMOD, and PMMPLLnPDIV registers specify the M, N, and P divisors which control the

operation of the PLL. The N divisor has an integer part specified in the PMMPLLnNDIV register and a

fractional part specified in the PMMPLLnNMOD register.

Clock Generation

Submit Documentation Feedback

Product Folder Links :CP3SP33

CP3SP33SMS/NOPB Datasheet(PDF) 81 Page - Texas Instruments

CP3SP33SMS/NOPB Datasheet(HTML) 81 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL