CP3SP33SMSSLASHNOPB datasheet(60/407 Pages) TI1

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CP3SP33

SNOSCW5 – MAY 2013

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12.3.3 Auto-Initialize Mode

This mode causes the DMA channel to repeat the same operation continuously without software

intervention. The operation is repeated until the channel is disabled.

12.3.3.1 Initialization

1. Select the peripheral device by writing the SRCRQ field in the DMACNTn register.

2. Write the block addresses and byte count into the ADCAn, ADCBn, and BLTCn counters, as well as

the ADRAn, ADRBn, and BLTRn registers.

3. Set the DMACNTn.OT bit to select auto-initialize mode.

4. Set the DMACNTn.CHEN bit to activate the channel and enable it to respond to DMA transfer

requests. If the DMACNTn register is loaded for any other reason, the DMACNTn.CHEN bit must be

clear to avoid prematurely starting a new DMA transfer.

12.3.3.2 Continuation

When the BLTCn counter reaches 0 (DMACNTn.PF = 0) or the last request has been processed

(DMACNTn.PF = 1):

1. The contents of the ADRAn, ADRBn, and BLTRn registers are copied to the ADCAn, ADCBn, and

BLTCn counters.

2. The DMAC channel checks the value of the DMASTAT.TC bit.

If the DMASTAT.TC bit is set and the DMACNTn.PF bit is clear:

1. The DMASTAT.OVR bit is set.

2. If enabled by the DMACNTn.EOVR bit, an interrupt is asserted.

3. The DMAC operation is repeated.

If the DMASTAT.TC and DMACNTn.PF bits are clear:

1. The DMASTAT.TC bit is set.

2. If enabled by the DMACNTn.ETC bit, an interrupt is asserted.

3. The DMAC operation is repeated.

12.3.3.3 Termination

The DMA transfer is terminated when the DMACNTn.CHEN bit is cleared.

12.4 Software DMA Request

In addition to the hardware requests from peripherals, a DMA transfer request can also be initiated by

software. A software DMA transfer request is used for memory-to-memory block transfers.

When the DMACNTn.SWRQ bit is set, the corresponding DMA channel receives a software DMA request.

When the DMACNTn.SWRQ bit is clear, the software DMA request for the channel is inactive.

A software DMA request may only be asserted when the associated peripheral DMA request is disabled

and the channel is inactive. Software can poll the DMASTAT.CHAC bit to determine whether the channel

is currently active.

When the DMACNTn.DIR bit is 0, the first bus cycle reads data from the source using the ADCAn counter,

while the second bus cycle writes the data into the destination using the ADCBn counter. When the

DMACNTn.DIR bit is set, the first bus cycle reads data from the source using the ADCBn counter, while

the second bus cycle writes the data into the destination addressed by the ADCAn counter.

CPU DMA Controller

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