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CP3SP33SMS/NOPB Datasheet(PDF) 84 Page - Texas Instruments

Part # CP3SP33SMS/NOPB
Description  Connectivity Processor with Cache, DSP, and Bluetooth짰, USB, and Dual CAN Interfaces
PDF  407 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

CP3SP33SMS/NOPB Datasheet(HTML) 84 Page - Texas Instruments

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CP3SP33
SNOSCW5 – MAY 2013
www.ti.com
Table 14-4. Recommended Audio Clock Divisors (continued)
FS
FIN
SOURCE
M Div.
N Div.
N Mod.
P Div.
(kHz)
(MHz)
System
44.1
16.2
5
30
20
9
System
44.1
16.8
4
26
8
10
System
44.1
19.2
4
26
8
10
System
44.1
19.44
6
30
20
9
System
44.1
19.8
6
36
24
11
System
48
11
4
48
0
11
System
48
12
4
40
0
10
System
48
12.288
6
46
28
8
System
48
13
13
96
0
8
System
48
14.4
6
40
0
8
System
48
16.2
6
40
0
9
System
48
16.8
7
40
0
8
System
48
19.2
6
30
0
8
System
48
19.44
9
50
0
9
System
48
19.8
6
40
0
11
I2S
48
1.536
1
78
4
10
I2S
44.1
1.4112
1
78
4
10
BT/USB
11.025
12
4
36
24
40
BT/USB
32
12
4
32
0
12
GSM
22.05
13
21
102
16
21
14.5 HCLK Clock
HCLK Clock drives the CPU and the modules on the CPU core AHB bus. It is generated by a 12-bit
prescaler from Main Clock, PLL1 Clock, or PLL2 Clock. The prescaler allows setting the HCLK Clock
period to any length between 1 and 2048 periods of the clock source, in increments of 1/2 period. The
default setting for the HCLK Clock period is 16 clock source periods.
Software may configure Slow Clock to drive HCLK Clock during Power Down and Idle modes.
14.6 PCLK Clock
PCLK Clock drives the modules on the peripheral APB bus. It is generated by a 2-bit prescaler from HCLK
Clock, for a division factor of 1, 2, or 4. The default is 1. The maximum PCLK Clock frequency is 48 MHz.
14.7 Auxiliary Clocks
Independent clocks are available for certain peripherals that may require clock frequencies different from
those provided as global clocks. An auxiliary clock also may be used for peripherals that require
independence from the clock-switching mechanism applied to HCLK Clock and PCLK Clock during low-
power modes. Eight auxiliary clock generators are provided for these peripherals. Some peripherals have
clock multiplexers to allow selection among several available clock sources.
Each auxiliary clock generator has an input multiplexer for selecting an input clock source:
•
Main Clock
•
PLL1 Clock
•
PLL2 Clock
84
Clock Generation
Copyright © 2013, Texas Instruments Incorporated
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