CP3SP33SMSSLASHNOPB datasheet(51/407 Pages) TI1

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CP3SP33

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SNOSCW5 – MAY 2013

10.4.4 Static Memory Timing Register n (SMTMGR_SETn)

The SMTMGR_SETn registers are 32-bit, read/write registers that specify timing parameters that can be

selected by the REG_SEL field in the SMSKRn registers. Any SMSKRn register may select any

SMTMGR_SETn register. At reset, the SMTMGR_SET0 register is initialized to 0002 0D45h, the

SMTMGR_SET1 register is initialized to 0012 0D45h, and the SMTMGR_SET2 register is initialized to

001A 0D45h. The register format is shown below.

30 29

28 27

26 25

19 18

16 15

10 9

8 7

6 5

Res.

SMRP

Res.

T_PRC

T_BTA

T_WR

T)AS

T_RC

The tRC field + 1 specifies the number of HCLK Clock cycles in a read cycle

T_AS

The tAS field specifies the number of HCLK Clock cycles in the write address setup time.

00 – Reserved.

01 – 1 cycle.

10 – 2 cycles.

11 – 3 cycles.

T_WR

The tWR field specifies the number of HCLK Clock cycles in the write address data hold time.

T_WP

The tWP field + 1 specifies the number of HCLK Clock cycles in a write pulse.

T_BTA

The tBTA field + 1 specifies the number of HCLK Clock cycles in the bus turnaround time. The

same value is used for read-to-write and write-to-read turnaround.

T_PRC

The tPRC field + 1 specifies the number of HCLK Clock cycles in the page-mode read cycle

time.

The Page Mode bit specifies whether page mode is used to access the device

0 – Page mode disabled.

1 – Page mode enabled.

The Page Size field specifies the page size. If the page size is larger than 64 bytes, the PS

field should be set to 11b.

00 – 8 bytes.

01 – 16 bytes.

10 – 32 bytes.

11 – 64 bytes.

SMRP

The Static Memory Read Pipe field specifies the number of registers inserted into the read data

path for correctly latching the data.

10.4.5 Flash tRPD Timing Register (FLASH_TRPDR)

The FLASH_TRPDR register is a 32-bit, read/write register that specifies the number of clock cycles

between flash memory reset/power-down and the first flash read/write cycle. At reset, the FLASH_TRPDR

12M M11

Reserved

T_RPD

The tRPD field + 1 specifies the number of clock cycles between flash memory reset/ power-

down and the first flash memory read/ write cycles. At reset, the default is 201 cycles

(value = C8h = 200d).

External Bus Interface Unit

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