CP3SP33SMSSLASHNOPB datasheet(92/407 Pages) TI1

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CP3SP33

SNOSCW5 – MAY 2013

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14.8.14 Auxiliary Clock n Prescaler Register (PMMAUXnPRSC)

The PMMAUXnPRSC registers are 16-bit read/write registers that hold the 12-bit clock divisors

(expressed in halfclocks) for the prescalers used to generate the corresponding Auxiliary Clocks from

Main Clock, PLL1 Clock, or PLL2 Clock (as selected by the PMMAUXnCTL.AUXCLKSRC field). The

registers are initialized to 00FFh at reset, except PMMAUX7PRSC which is initialized to 0001h.

12M M11

Reserved

HPACLK

The Half Periods Per Auxiliary Clock field specifies the number of half-clocks used for

generating the Auxiliary Clock. The clock source is divided by

((HPACLK + 1) ÷ 2) to obtain the auxiliary clock. Zero is an undefined value for this field.

15 Reset

There are five sources of reset:

•

Power-On Reset—on-chip power-on detector and timer.

•

External Reset—assertion of the RESET input.

•

Software Reset—enabled by writing special code sequences to the SWRESET register.

•

Timing and Watchdog Module (TWM)—overflow of the watchdog timer

•

SDI Reset—reset from the Serial Debug Interface (SDI)

15.1 Power-On Reset

The on-chip Power On Reset (POR) circuit generates a positive edge on the internal reset signal when

VCC rises above VTRIP (typically 1.38V). The VCC rise time from 0V to VTRIP must not exceed the

maximum tTRIP specification. After triggering the POR circuit, the rise time from VTRIP to a stable VCC must

not exceed the maximum tD specification. After reset has occurred, the POR is specified to rearm when

VCC falls below 400 mV (although it may rearm at a higher voltage, up to 600 mV), and it will be

retriggered when VCC again rises above VTRIP. There must be a delay of at least 950 µs before

retriggering the POR.

VCC ramp-up must reach its nominal level before or simultaneous with IOVCC ramp-up, otherwise spikes

may be driven on GPIO-capable pins.

15.2 Reset Input Timing

The CP3SP33 has specific timing requirements that must be met to prevent improper program behavior,

such as corruption of an external flash memory programming operation in progress when the reset is

received. This timing sequence shown in Figure 15-1.

All reset circuits must ensure that this timing sequence is always maintained during power-up and power-

down. The design of the power supply also affects how this sequence is implemented.

The power-up sequence is:

1. The RESET pin must be held low until both IOVCC and VCC have reached the minimum levels

specified in the DC Characteristics section. VCC must reach its nominal level at or before IOVCC.

2. After both of these supply voltage rails have met this condition, then the RESET pin may be driven

high. At power-up an internal 14-bit counter is set to 3FFFh and begins counting down to 0 after the

crystal oscillator becomes stable. When this counter reaches 0, the onchip RESET signal is driven high

unless the external RESET pin is still being held low. This prevents the CP3SP33 from coming out of

reset with an unstable clock source.

The power-down sequence is:

1. The RESET pin must be driven low as soon as either the IOVCC or VCC voltage rail reaches the

minimum levels specified in the DC Characteristics.

Reset

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