CP3SP33SMSSLASHNOPB datasheet(58/407 Pages) TI1

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CP3SP33

SNOSCW5 – MAY 2013

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12.2.1 DMA Buffer Flush

When data collection mode has been used to read data from a peripheral, the number of bytes received

from the peripheral might not correspond to an integral number of bursts. To flush data remaining in the

buffer, perform the following steps:

1. Disable the peripheral DMA request. Do not clear the DMA channel enable bit (the CHEN bit in the

DMACNTn register), because clearing this bit will clear the buffer.

2. Read the BNE bit and the BLV field in the DMASTATn register. The BNE bit indicates whether there is

valid data in the buffer. The BLV field indicates the number of valid bytes in the buffer.

3. Clear the BBE bit in the DMACNTn register. This enables a burst write to memory, even though the

buffer is not full. Invalid entries in the buffer are written to memory with undefined data.

A buffer flush will only occur when the DIR bit in the DMACNTn register is clear, and the buffer is not

empty (the BNE bit in the DMASTATn register is set). If the DIR bit is set, the data in the buffer is

discarded.

12.3 Transfer Modes

A DMAC channel may be used in one of three different transfer modes:

•

Single Buffer—The transfer performed for the channel is specified by the states sampled from the

control registers when the last DMA request was enabled.

•

Double Buffer—The transfer performed for the channel is specified by the states sampled from the

control registers when the last DMA request was enabled. A new set of states is loaded into the control

registers to specify the next transfer to be performed for the channel.

•

Auto-initialize—The transfer performed for the channel is specified in its control registers, and the

operation is repeated as long as the channel is enabled.

The OT bit in the DMACNTn register is clear for single buffer and double buffer mode. The OT bit is set to

enable auto-initialize mode.

Double buffer mode is obtained by reloading the DMAC channel control registers after a DMA request has

been enabled. A DMA request is enabled by loading the DMACNTn register with a set CHEN bit. After

enabling a DMA request, the DMA control registers may be loaded with new states. The BLTRn register

must be written last, because loading this register sets the VLD bit in the DMASTATn register, which

indicates that new values have been loaded into the control registers.

When the PF bit in the DMACNTn register is clear, the DMAC is the flow controller for the transfer. When

the PF bit is set, the peripheral is the flow controller. In double buffer mode with the peripheral as the flow

controller, the BLTRn register must be written so that the VLD bit becomes set, even though the value in

the BLTRn register is not used.

12.3.1 Single Buffer Mode

This mode provides the simplest way to accomplish a single data transfer.

12.3.1.1 Initialization

1. Select the peripheral device by writing the SRCRQ field in the DMACNTn register.

2. Write the block transfer addresses and byte count into the corresponding ADCAn, ADCBn, and BLTCn

counters.

3. Clear the DMACNTn.OT bit to select non-auto-initialize mode. Clear the DMASTAT.VLD bit by writing

a 1 to it.

4. Set the DMACNTn.CHEN bit to activate the channel and enable it to respond to DMA transfer

requests. If the DMACNTn register is loaded for any other reason, the DMACNTn.CHEN bit must be

clear to avoid prematurely starting a new DMA transfer.

CPU DMA Controller

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