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CP3SP33SMS/NOPB Datasheet(PDF) 26 Page - Texas Instruments |
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CP3SP33SMS/NOPB Datasheet(HTML) 26 Page - Texas Instruments |
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26 / 407 page  CP3SP33 SNOSCW5 – MAY 2013 www.ti.com Table 5-2. Instruction Set Summary (continued) MNEMONIC OPERANDS DESCRIPTION LOADD disp(Rbase), Rdest Load (register relative) abs, Rdest Load (absolute) (Rindex)abs, Rdest Load (absolute index relative) (Rindex)disp(RPbasex), Rdest Load (register pair relative index) disp(RPbase), Rdest Load (register pair relative) STORi Rsrc, disp(Rbase) Store (register relative) Rsrc, disp(RPbase) Store (register pair relative) Rsrc, abs Store (absolute) Rsrc, (Rindex)disp(RPbasex) Store (register pair relative index) Rsrc, (Rindex)abs Store (absolute index) STORD RPsrc, disp(Rbase) Store (register relative) RPsrc, disp(RPbase) Store (register pair relative) RPsrc, abs Store (absolute) RPsrc, (Rindex)disp(RPbasex) Store (register pair index relative) RPsrc, (Rindex)abs Store (absolute index relative) STOR IMM imm4, disp(Rbase) Store unsigned 4-bit immediate value extended to operand length in memory imm4, disp(RPbase) imm4, (Rindex)disp(RPbasex) imm4, abs imm4, (Rindex)abs LOADM imm3 Load 1 to 8 registers (R2-R5, R8-R11) from memory starting at (R0) LOADMP imm3 Load 1 to 8 registers (R2-R5, R8-R11) from memory starting at (R1, R0) STORM STORM imm3 Store 1 to 8 registers (R2-R5, R8-R11) to memory starting at (R2) STORMP imm3 Store 1 to 8 registers (R2-R5, R8-R11) to memory starting at (R7,R6) DI Disable maskable interrupts EI Enable maskable interrupts EIWAIT Enable maskable interrupts and wait for interrupt NOP No operation WAIT Wait for interrupt CINV [i] Invalidate instruction cache 26 CPU Architecture Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links :CP3SP33 |
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