CP3SP33SMSSLASHNOPB datasheet(66/407 Pages) TI1

66 / 407 page

CP3SP33

SNOSCW5 – MAY 2013

www.ti.com

INCA

WMODE

TCS

Step Size

-1

-2

-4

If the Device B Address Control bit is set, it enables updating the Device B Address.

0 – ADCBn address unchanged.

1 – ADCBn address incremented or decremented, as controlled by the INCB field and

WMODE and TCS bits.

INCB

The Increment/Decrement ADCBn field specifies the step size for the Device B address

increment/decrement.

INCB

WMODE

TCS

Step Size

-1

-2

-4

WMODE

The 32-bit Word Mode bit controls whether the transfer cycle size is 32 bits. If set, it

overrides the TCS bit.

0 – Transfer cycle size selected by the TCS bit.

1 – Transfer cycle size is 32 bits.

BBE

The Burst Buffer Enable bit controls whether Single transfer type or data collection/burst

transfer type is used. Only channels 0 and 1 have burst buffers. For the other channels, the

BBE bit is reserved.

0 – Single transfer type.

1 – Data collection or burst transfer type.

The Peripheral Flow bit controls whether the DMAC or the peripheral is the flow controller.

0 – The DMAC is the flow controller. The DMA transfer is terminated when the BLTCn

1 – The peripheral is the flow controller.

HPROT

The HPROT field must be 0011b (default value).

TOEN

The Enable Timeout bit controls whether DMA request timeout monitoring is enabled.

0 – Timeout disabled.

1 – Timeout enabled.

SRCRQ

The Source Request field specifies a peripheral register used as the source or destination for

a DMA transfer.

CPU DMA Controller

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