CP3SP33SMSSLASHNOPB datasheet(42/407 Pages) TI1

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CP3SP33

SNOSCW5 – MAY 2013

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9.3.8

CPU Interrupt Mask Register (PMASK)

The PMASK register is a 16-bit, read/write register used by the CPU to mask interrupt requests from the

DSP. If the DSP sets a bit in the APBP_SEM register and the corresponding bit in the PMASK register is

clear, the CPU is interrupted. After reset, this register is clear.

PMASK

9.3.9

CPU-to-DSP Semaphore Clear Register (PCLEAR)

The PCLEAR register is a 16-bit, write-only register used by the CPU to clear interrupt requests from the

DSP. Writing 1 to bits in the PCLEAR register clears the corresponding bits in the APBP_SEM register.

PCLEAR

9.3.10 DSP-to-CPU Semaphore Register (APBP_SEM)

The APBP_SEM register is a 16-bit, read-only register which indicates interrupt requests from the DSP.

When the DSP sets a bit in this register while the corresponding bit in the PMASK register is clear, an

interrupt is asserted to the CPU. After reset, this register is clear.

APBP_SEM

9.3.11 CPU-to-DSP Command Register n (APBP_COMn)

The APBP_COMn registers are 16-bit registers that are read/write to the CPU and read-only to the DSP

(as MMIO registers). After reset, these registers are clear.

APBP_COMn

9.3.12 DSP-to-CPU Reply Register n (APBP_REPn)

The APBP_REPn registers are 16-bit registers that are read/write to the DSP (as MMIO registers) and

read-only to the CPU. After reset, these registers are clear.

APBP_REPn

9.3.13 ASC DMA Controller Select Register n (ASCDMASELn)

The ASCDMASELn registers are 16-bit, read/write registers that select between the CPU and DSP DMA

controllers for the ASC DMA channels (listed in Table 9-4). Bits 15:0 of ASCDMASEL0 correspond to ASC

DMA channels 15:0, and bits 4:0 of ASCDMASEL1 correspond to ASC DMA channels 20:16. Clear bits

select the CPU DMA controller, and set bits select the DSP DMA controller. After reset, these registers are

clear.

DCH15:0

DSP and Audio Peripherals

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