CP3SP33SMSSLASHNOPB datasheet(94/407 Pages) TI1

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GND

IOVCC

RESET

DS491

CP3SP33

IOVCC

LM3724

5-Pin Reset

Circuit

N Ÿ

Manual

Reset

SDI Reset

GND

IOVCC

RESET

DS489

CP3SP33

IOVCC

LM809

3-Pin Reset

Circuit

CP3SP33

SNOSCW5 – MAY 2013

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Figure 15-2. Simple External Reset

15.2.2 Manual and SDI External Reset

An external reset circuit based on the LM3724 5-Pin Microprocessor Reset Circuit is shown in Figure 15-3.

The LM3724 produces a 190-ms logic low reset pulse when the power supply rises above a threshold

voltage or a manual reset button is pressed. Various reset thresholds are available for the LM3724,

however the option for 3.08V is most suitable for a CP3SP33 device operating from an IOVCC at 3.3V.

Figure 15-3. Manual and SDI External Reset

The LM3724 provides a debounced input for a manual pushbutton reset switch. It also has an open-drain

output which can be used for implementing a wire-OR connection with a reset signal from a serial debug

interface. This circuit is typical of a design to be used in a development or evaluation environment,

however it is a good recommendation for all general CP3SP33 designs. If an SDI interface is not

implemented, an LM3722 with active pullup may be used.

Reset

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CP3SP33SMS/NOPB Datasheet(PDF) 94 Page - Texas Instruments