CP3SP33SMSSLASHNOPB datasheet(99/407 Pages) TI1

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Reset

Active Mode

HALT = 1 &

WBPSM = 1 &

"WAIT"

IDLE = 1 & "WAIT"

HW Event

or PSM = 1 & DHC = 0 & DMC = 0

HW Event

Note:

HW Event = MIWU wake-up,

NMI, or

interrupt acknowledge while PMMSTCTL.WACK = 1

HALT = 1 & "WAIT"

PSM = 1 &WBPSM = 0

or PSM = 1 & WBPSM = 1 & "WAIT"

Power Save Mode

Idle Mode

Halt Mode

DS444

CP3SP33

www.ti.com

SNOSCW5 – MAY 2013

Figure 16-1. Power Mode State Diagram

Software changes the power mode in either of two ways, as controlled by the PMMSTCTL.WBPSM bit:

•

Immediate transition (WBPSM = 0)—new clock sources take effect as soon as stable clocks are

available. Only allowed when going from Active to Power Save mode.

•

Transition at next WAIT instruction (WBPSM = 1)—device continues to operate in Active mode until it

executes a WAIT instruction. At execution of the WAIT instruction, the device enters the new mode,

and the CPU waits for the next interrupt event.

A transition to Idle or Halt mode must use the second method (WBPSM = 1).

Some of the power-up transitions are based on the occurrence of a wake-up event:

•

Multi-Input Wake-Up Event—most general-purpose I/O port pins, certain peripheral pins (that don’t

share functionality with a GPIO port), and certain peripheral events can be programmed in the MIWU

module to trigger a wake-up event.

•

Non-Maskable Interrupt (NMI)—an NMI interrupt is a wake-up event.

•

Interrupt Acknowledge Cycle—when the WACK bit in the PMMSTCTL register is set, any interrupt

acknowledge cycle is a wake-up event.

Once a wake-up event is detected, it is latched until an interrupt acknowledge cycle or reset occurs.

A wake-up event causes a transition to the Active mode and restores normal clock operation, but does not

start execution of the program. It is the interrupt handler associated with the wake-up source (MIWU, NMI,

or any interrupt) that causes program execution to resume.

16.6.1 Active Mode to Power Save Mode

A transition from Active mode to Power Save mode is performed by writing a 1 to the PMMSTCTL.PSM

bit. The transition to Power Save mode occurs immediately or at the execution of the next WAIT

instruction, depending on the state of the PMMSTCTL.WBPSM bit. The PSM bit operates differently

depending on this mode:

•

WBPSM = 0—PSM bit reads as 1 after the transition to the Power Save mode occurs. If the high-

frequency oscillator or PLLs are not producing a stable output, this transition may be stalled. In this

mode, the PSM bit indicates when the transition has been completed.

•

WBPSM = 1—PSM bit reads as 1 after it is written with 1, even before the WAIT instruction has

executed and the transition to Power Save mode has occurred.

Power Management Module

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