CP3SP33SMSSLASHNOPB datasheet(101/407 Pages) TI1

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CP3SP33

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SNOSCW5 – MAY 2013

The PMMSR.MCLKSTB, PMMSR.SCLKSTB, and PMMPLLnCTL2.PLLCLKSTB bits indicate the current

status of the high-frequency oscillator, low-frequency oscillator, and PLLs, respectively. Software can

check the appropriate bit before switching to a power mode that requires a specific clock. A set bit

indicates an operating, stable clock. A clear bit indicates a clock that is disabled, not available, or not yet

stable.

During a power mode transition, if there is a request to switch to a mode which uses a clock with a clear

stability bit, the switch is delayed until the bit is set by the hardware.

When the system is built without an external crystal network for the low-frequency clock, Main Clock or a

PLL Clock is divided by a prescaler to produce the low-frequency clock. In this situation, Main Clock is

disabled only in the Halt mode, and cannot be disabled for the Power Save or Idle mode.

Following reset, Main Clock drives Slow Clock through a prescaler. The prescaler value results in a Slow

Clock rate of 32.786.885 Hz.

NOTE

For correct operation in the absence of a low-frequency crystal, the X2CKI pin must be tied

low (not left floating) so that the hardware can detect the absence of the crystal.

16.7 Power Management Register

Table 16-3 shows the power management register.

Table 16-3. Power Management Register

NAME

ADDRESS

DESCRIPTION

PMMSTCTL

FF A404h

Power Management State Control Register

16.7.1 Power Management State Control Register (PMMSTCTL)

The PMMSTCTL register is a byte-wide, read/write register that controls the operating power mode

(Active, Power Save, Idle, or Halt) and enables or disables the high-frequency oscillator in the Power Save

and Idle modes. At reset, the register are cleared. The format of the register is shown below. At reset, the

DSC

WACK

HCCM

DMC

WBPSM

HALT

IDLE

PSM

When the Power Save Mode bit is clear, the system is in Active mode. If the WBPSM bit is

clear, writing 1 to the PSM bit causes the device to start the switch to Power Save mode. If

the WBPSM bit is set when the PSM bit is written with 1, entry into Power Save mode is

delayed until execution of a WAIT instruction. The PSM bit becomes set after the switch to

Power Save mode is complete. The PSM bit can be cleared by software, and it can be cleared

by hardware when a hardware wakeup event is detected.

0 – Device is not in Power Save mode.

1 – Device is in Power Save mode.

IDLE

The Idle Mode bit indicates whether the device has entered Idle mode. If the WBPSM bit is

clear and the device is in Power Save mode, writing 1 to the IDLE bit causes the device to

start the switch to IDLE mode. If the WBPSM bit is set when the IDLE bit is written with 1,

entry into Idle mode is delayed until execution of a WAIT instruction. The IDLE bit can be set

and cleared by software. It is also cleared by hardware when a hardware wake-up event is

detected. When set, the IDLE bit overrides the PSM bit.

0 – Device is not in Idle mode.

1 – Device is in Idle mode.

Power Management Module

101

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