TMS320F28375DPZP datasheet(102/222 Pages) TI1

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VREFHI

VREFLO

(VSSA)

VREFHI/2

Pin Voltage

ADCINx

ADC

ADCINx

VREFLO

VREFHI

n - 1

Digital Output

ADC Vin

102

TMS320F28379D, TMS320F28378D, TMS320F28377D

TMS320F28376D, TMS320F28375D, TMS320F28374D

SPRS880K – DECEMBER 2013 – REVISED NOVEMBER 2018

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Product Folder Links: TMS320F28379D TMS320F28378D TMS320F28377D TMS320F28376D TMS320F28375D

TMS320F28374D

Specifications

Figure 5-32. Single-ended Signaling Mode

5.10.1.2 ADC Electrical Data and Timing

Table 5-42 shows the ADC operating conditions for 16-bit differential mode. Table 5-43 shows the ADC

characteristics for 16-bit differential mode. Table 5-44 shows the ADC operating conditions for 12-bit

single-ended mode. Table 5-45 shows the ADC characteristics for 12-bit single-ended mode. Table 5-46

shows the ADCEXTSOC timing requirements.

(1)

The sample window must also be at least as long as 1 ADCCLK cycle for correct ADC operation.

(2)

VREFCM = (VREFHI + VREFLO)/2

(3)

The VREFCM requirements will not be met if the negative ADC input pin is connected to VSSA or VREFLO.

Table 5-42. ADC Operating Conditions (16-Bit Differential Mode)

over recommended operating conditions (unless otherwise noted)

MIN

TYP

MAX

UNIT

ADCCLK (derived from PERx.SYSCLK)

MHz

Sample window duration (set by ACQPS and PERx.SYSCLK)(1)

320

VREFHI

2.4

2.5 or 3.0

VDDA

VREFLO

VSSA

VREFHI – VREFLO

2.4

VDDA

ADC input conversion range

VREFLO

VREFHI

ADC input signal common mode voltage(2)(3)

VREFCM – 50

VREFCM

VREFCM + 50

NOTE

The ADC inputs should be kept below VDDA + 0.3 V during operation. If an ADC input

exceeds this level, the VREF internal to the device may be disturbed, which can impact results

for other ADC or DAC inputs using the same VREF.

TMS320F28375DPZP Datasheet(PDF) 102 Page - Texas Instruments

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