H5GQ2H24AFR-R0C datasheet(54/172 Pages) HYNIX

Part #	H5GQ2H24AFR-R0C

Description	2Gb (64Mx32) GDDR5 SGRAM

PDF	172 Pages

Scroll/Zoom	100%

Manufacturer	HYNIX [Hynix Semiconductor]

Direct Link	http://www.skhynix.com/kor/main.do

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54 / 172 page

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.2 /Nov. 2011

H5GQ2H24AFR

Read CRC

Bit A9 controls the CRC calculation for READ bursts. When enabled, the calculated CRC pattern will be

transmitted on the EDC pins with the latency as programmed in the CRCRL field of this register. With

Read CRC being off, no CRC will be calculated for READ bursts, and the EDC hold pattern will be

transmitted instead.

Write CRC

Bit A10 controls the CRC calculation for WRITE bursts. When enabled, the calculated CRC pattern will be

transmitted on the EDC pins with the latency as programmed in the CRCWL field of this register. With

Write CRC being off, no CRC will be calculated for WRITE bursts, and the EDC hold pattern will be trans‐

mitted instead.

H5GQ2H24AFR-R0C Datasheet(PDF) 54 Page - Hynix Semiconductor