H5GQ2H24AFR-R0C datasheet(67/172 Pages) HYNIX

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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.2 /Nov. 2011

H5GQ2H24AFR

5.2. DESELECT (NOP)

The DESELECT function (CS# HIGH) prevents new commands from being executed by the GDDR5

SGRAM. The GDDR5 SGRAM is effectively deselected. Operations already in progress are not affected.

5.3. NO OPERATION (NOP)

The NO OPERATION (NOP) command is used to instruct the selected GDDR5 SGRAM to perform a NOP

(CS# LOW). This prevents unwanted commands from being registered during idle or wait states. Opera‐

tions already in progress are not affected.

5.4. MODE REGISTER SET

The MODE REGISTER SET command is used to load the Mode Registers of the GDDR5 SGRAM. The bank

address inputs BA0‐BA3 select the Mode Register, and address puts A0‐A11(A12) determine the op‐code

to be loaded. See MODE REGISTER for a register definition. The MODE REGISTER SET command can

only be issued when all banks are idle and no bursts are in progress, and a subsequent executable com‐

mand cannot be issued until tMRD is met.

Figure 37. MRS Command

LOW

RA = Row Address

CO = Op‐code

BA = Bank Address

EN AP = Enable Auto Precharge

DIS AP = Disable Aut o Precharge

Mode Register Set

CS#

WE#

CAS#

RAS#

CKE#

CK#

DONʹT CARE

BA0‐BA3

A2‐A5

BA0,1,2,3

A2,3,4,5

A8,9,10,11, (12)

A0,1,6,7

A8‐A11 (A12)

A0,A1,A6,A7

H5GQ2H24AFR-R0C Datasheet(PDF) 67 Page - Hynix Semiconductor