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H5GQ2H24AFR-R0C Datasheet(PDF) 55 Page - Hynix Semiconductor

Part # H5GQ2H24AFR-R0C
Description  2Gb (64Mx32) GDDR5 SGRAM
PDF  172 Pages
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Manufacturer  HYNIX [Hynix Semiconductor]
Direct Link  http://www.skhynix.com/kor/main.do
Logo HYNIX - Hynix Semiconductor

H5GQ2H24AFR-R0C Datasheet(HTML) 55 Page - Hynix Semiconductor

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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.2 /Nov. 2011
55
H5GQ2H24AFR
 4.6. MODE REGISTER 5 (MR5)
Mode Register 5 defines digital RAS, PLL band‐width and low power modes as shown in Figure 29.
The register is programmed via the MODE REGISTER SET (MRS) command with BA0=1, BA1=0, BA2=1 
and BA3=0.
Figure 29. Mode Register 5 (MR5) Definition
A1
LP2
0Off
1On
BA3 BA2 BA1 BA0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
01
010
RFU
PLL Bandwidth
LP3
LP2
RFU
A5
A4
A3
‐3dB [MHz]
BW3dBLL
Peak [MHz]
BWPKLL
Peak [dB]
PKLL
00
0
22
6
＜ 2.14
00
1
45
9
＜ 2.14
01
0
55
14
＜1.58
01
1
60
17
＜1.87
10
0
65
21
＜1.87
10
1
70
26
＜1.87
11
0
80
33
＜1.87
11
1
85
35
＜ 2.14
A2
LP3
0Off
1On
Note 1) PLL BW characteristics is measured at 5Gbps
Note 2) PLL BW is linearly proportional to the data rate
Note 3) -3dB frequency is approximately interpolated from simulation
& measurement



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