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H5GQ2H24AFR-R0C Datasheet(PDF) 79 Page - Hynix Semiconductor

Part # H5GQ2H24AFR-R0C
Description  2Gb (64Mx32) GDDR5 SGRAM
PDF  172 Pages
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Manufacturer  HYNIX [Hynix Semiconductor]
Direct Link  http://www.skhynix.com/kor/main.do
Logo HYNIX - Hynix Semiconductor

H5GQ2H24AFR-R0C Datasheet(HTML) 79 Page - Hynix Semiconductor

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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.2 /Nov. 2011
79
H5GQ2H24AFR
Figure 49. WRITE to READ
2.  WCK and CK are shown aligned (tWCK2CKPIN=0, tWCK2CK=0) for illustration purposes.  WCK2CK training determines the needed offset between WCK and CK.
DO
DO
m+7
m
CL = CLmrs = 6
WL = WLmrs = 3
DBI
DBI
n+7
n
Bank a,
Col m
Col m
Ta0
Ta7
Ta8
T0
T1
T3
T4
T4n
T5
Ta6
Ta6n
DO
DO
n+7
n
Bank b,
Col n
Col n
tWTR
respectively must be met.
DBI
DBI
m+7
m
T3n
1.  WLmrs = 3 and CLmrs = 6 is shown as an example.  Actual supported values will be found in the MR and AC timings sections.
3.  EDC may be on or off.  See Figure 4 for EDC Timing.
5.  For WRITE operations it is important that the latching point meet the data valid window requirements, which may or may not be center aligned at the pins. 
6.  Before the READ and WRITE commands, an ACTIVE (ACT) command is required to be issued to the GDDR5 SGRAM and tRCDRD or tRCDWR
4.  tWTR = tWTRL when bank groups is enabled and both WRITE and READ access banks in the same bank group, otherwise tWTR=tWTRS.
Notes:
7.  tWCK2DQI, tWCKDQO = 0 is shown for illustration purposes.
DONʹT CARE
TRANSITIONING DATA
NOP
WRITE
NOP
NOP
NOP
READ
NOP
NOP
NOP
CK
CK#
ADDRESS
DQ
DBI#
WCK#
WCK
COMMAND
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