Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

Preview PDF HTML

H5GQ2H24AFR-R0C Datasheet(PDF) 95 Page - Hynix Semiconductor

Part # H5GQ2H24AFR-R0C
Description  2Gb (64Mx32) GDDR5 SGRAM
PDF  172 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  HYNIX [Hynix Semiconductor]
Direct Link  http://www.skhynix.com/kor/main.do
Logo HYNIX - Hynix Semiconductor

H5GQ2H24AFR-R0C Datasheet(HTML) 95 Page - Hynix Semiconductor

Back Button H5GQ2H24AFR-R0C Datasheet HTML 91Page - Hynix Semiconductor H5GQ2H24AFR-R0C Datasheet HTML 92Page - Hynix Semiconductor H5GQ2H24AFR-R0C Datasheet HTML 93Page - Hynix Semiconductor H5GQ2H24AFR-R0C Datasheet HTML 94Page - Hynix Semiconductor H5GQ2H24AFR-R0C Datasheet HTML 95Page - Hynix Semiconductor H5GQ2H24AFR-R0C Datasheet HTML 96Page - Hynix Semiconductor H5GQ2H24AFR-R0C Datasheet HTML 97Page - Hynix Semiconductor H5GQ2H24AFR-R0C Datasheet HTML 98Page - Hynix Semiconductor H5GQ2H24AFR-R0C Datasheet HTML 99Page - Hynix Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 95 / 172 page
background image
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.2 /Nov. 2011
95
H5GQ2H24AFR
Figure 60. Gapless READs
CL = CLmrs = 6
Bank a,
Col m
Col m
CK
CK#
DQ
DBI#
WCK#
WCK
T7
T9
T10
T0
T1
T2
T3
T9n
T6
T6n
T7n
T8
T8n
DONʹT CARE
TRANSITIONING DATA
Bank b,
Col n
Col n
DO
DO
DBI
DBI
m+7
m+7
m
m
tCCD
DO
DO
n+7
n
DBI
DBI
n+7
n
2.  WCK and CK are shown aligned (tWCK2CKPIN=0, tWCK2CK=0) for illustration purposes.  WCK2CK training determines the needed offset between WCK and CK.
4.  tCCD = tCCDS when bank groups are disabled or the second READ is to a different bank group; otherwise tCCD=tCCDL. 
5.  Before the READ commands, an ACTIVE (ACT) command is required to be issued to the GDDR5 SGRAM and tRCDRD must be met.
1.  CLmrs = 6 is shown as an example.  Actual supported values will be found in the MR and AC timings sections.
3.  EDC may be on or off.  See Figure 58 for EDC Timing.
Notes:
6.  tWCK2DQI = 0 is shown for illustration purposes.
NOP
READ
READ
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
ADDRESS
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com