H5GQ2H24AFR-R0C datasheet(15/172 Pages) HYNIX

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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.2 /Nov. 2011

H5GQ2H24AFR

2. ADDRESS

2.1. ADDRESSING

GDDR5 SGRAMs use a double data rate address scheme to reduce pins required on the GDDR5 SGRAM

as shown in Table 5. The addresses should be provided to the GDDR5 SGRAM in two parts; the first half is

latched on the rising edge of CK along with the command pins such as RAS#, CAS# and WE#; the second

half is latched on the next rising edge of CK#.

The use of DDR addressing allows all address values to be latched in at the same rate as the SDR com‐

mands. All addresses related to command access have been positioned for latching on the initial rising

edge for faster decoding.

Note: Address pin A12 is required only for 2G density.

GDDR5 addressing includes support for 2G density. For all densities two modes are supported (x32 mode

or x16 mode). x32 and x16 modes differ only in the number of valid column addresses, as shown in Table6.

Table 5 Address Pairs

Clock

Address Pins

Rising CK

BA3

BA2

BA1

BA0

A12

A11

A10

Rising CK#

RFU

Table 6 Addressing Scheme

x32 mode

x16 mode

Row address

A0~A12

Column address

A0~A5

A0~A6

Bank address

BA0~BA3

Autoprecharge

Page Size

Refresh

16K/32ms

Refresh period

1.9us

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