H5GQ2H24AFR-R0C datasheet(30/172 Pages) HYNIX

30 / 172 page

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.2 /Nov. 2011

H5GQ2H24AFR

Example 2: outline of a basic WCK2CK training sequence with optional WCK clock stop:

Stop WCK clocks with WCK01/WCK23 LOW and WCK01#/WCK23# HIGH

Wait tWCK2MRS for internal WCK clocks to settle

Enable training mode via MRS and wait tMRD for divide‐by‐2 circuits to reset

Start WCK clocks without glitches (both divide‐by‐2 circuits remain in sync)

Wait tWCK2TR for internal WCK clocks to stabilize

Sweep and observe the phase independently for WCK01 on EDC0 and WCK23 on EDC2; adjust

the 

WCK phase to the optimal point (“ideal alignment”)

Issue a PLL reset and wait tLK (PLL on mode only)

While all WCK and CK are aligned, exit WCK2CK training mode via MRS

Wait tMRD for the reset of data synchronizers

READ and WRITE latency timings are defined relative to CK. Any offset in WCK and CK at the pins and/

or the phase detector will be reflected in the latency timings. The parameters used to define the relation‐

ship between WCK and CK are shown in Figure 6. For more details on the impact on READ and WRITE

timings see the OPERATIONS section.

Figure 15: WCK2CK Timings

CK#

tCH

tCL

tCK

WCK

WCK#

tWCK2CKPIN

Case 1: Negative tWCK2CKPIN; tWCK2CK = 0 (ideal WCK2CK alignment)

tWCK

WCK

WCK#

Case 2: Negative tWCK2CKPIN; negative tWCK2CK

WCK

WCK#

tWCK2CKPIN

Case 3: Positive tWCK2CKPIN; tWCK2CK = 0 (ideal WCK2CK alignment)

tWCK2CKPIN + tWCK2CK

WCK#

WCK

Case 4: Positive tWCK2CKPIN; positive tWCK2CK

tWCK2CKPIN + tWCK2CK

Note: tWCK2CKPIN and tWCK2CK parameter values could be negative or positive numbers, depending on the selected

WCK2CK alignment point, PLL‐on‐or PLL‐off mode operation and design implementation. They also vary across

PVT. WCK2CK training is required to determine the correct WCK‐to‐CK phase for stable device operation.

tWCKH tWCKL

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