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H5GQ2H24AFR-R0C Datasheet(PDF) 56 Page - Hynix Semiconductor

Part # H5GQ2H24AFR-R0C
Description  2Gb (64Mx32) GDDR5 SGRAM
PDF  172 Pages
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Manufacturer  HYNIX [Hynix Semiconductor]
Direct Link  http://www.skhynix.com/kor/main.do
Logo HYNIX - Hynix Semiconductor

H5GQ2H24AFR-R0C Datasheet(HTML) 56 Page - Hynix Semiconductor

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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.2 /Nov. 2011
56
H5GQ2H24AFR
Low Power Modes (LP2, LP3)
Bits A1‐A2 control several low power modes of the GDDR5 SGRAM. The modes are independent of each 
other.
When bit A1 (LP2) is set, the WCK receivers may be turned off during power‐down.
When bit A2 (LP3) is set, RDTR, WRTR and LDFF commands are not allowed while a REF command is 
being executed.
PLL Bandwidth
The PLL bandwidth may optionally be configured to match system characteristics. Each setting defines a 
unique combination of ‐3dB corner frequency, peaking frequency and peaking magnitude. 



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