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H5GQ2H24AFR-R0C Datasheet(PDF) 97 Page - Hynix Semiconductor

Part # H5GQ2H24AFR-R0C
Description  2Gb (64Mx32) GDDR5 SGRAM
PDF  172 Pages
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Manufacturer  HYNIX [Hynix Semiconductor]
Direct Link  http://www.skhynix.com/kor/main.do
Logo HYNIX - Hynix Semiconductor

H5GQ2H24AFR-R0C Datasheet(HTML) 97 Page - Hynix Semiconductor

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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.2 /Nov. 2011
97
H5GQ2H24AFR
Figure 62. READ to PRECHARGE
DO
DO
DBI
DBI
n+7
n+7
n
n
Bank a,
Col n
Col n
CK
CK#
DQ
DBI#
CL = CLmrs = 6
WCK#
WCK
T5
T7
T8
T0
T1
T2
T3
T4
T7n
T6
T6n
tRTP
Bank a,
or all
DONʹT CARE
TRANSITIONING DATA
tRP
2.  WCK and CK are shown aligned (tWCK2CKPIN=0, tWCK2CK=0) for illustration purposes. WCK2CK training determines the needed offset between WCK and CK.
4.  tRTP = tRTPL when bank groups are enabled and the PRECHARGE command accesses the same bank; otherwise tRTP = tRTPS. 
5.  Before the READ commands, an ACTIVE (ACT) command is required to be issued to the GDDR5 SGRAM and tRCDRD must be met.
1.  CLmrs = 6 is shown as an example.  Actual supported values will be found in the MR and AC timings sections.
3.  EDC may be on or off.  See Figure 58 for EDC Timing.
Notes:
6.  tWCK2DQO = 0 is shown for illustration purposes.
NOP
READ
PRE
NOP
NOP
NOP
NOP
NOP
NOP
ADDRESS
COMMAND



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