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H5GQ2H24AFR-R0C Datasheet(PDF) 45 Page - Hynix Semiconductor

Part # H5GQ2H24AFR-R0C
Description  2Gb (64Mx32) GDDR5 SGRAM
PDF  172 Pages
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Manufacturer  HYNIX [Hynix Semiconductor]
Direct Link  http://www.skhynix.com/kor/main.do
Logo HYNIX - Hynix Semiconductor

H5GQ2H24AFR-R0C Datasheet(HTML) 45 Page - Hynix Semiconductor

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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.2 /Nov. 2011
45
H5GQ2H24AFR
 4.2. MODE REGISTER 1 (MR1)
Mode Register 1 controls functions like drive strength, data termination, address/command termination, 
Read DBI, Write DBI, ABI, control of calibration updates and PLL as shown in Figure 24.
The register is programmed via the MODE REGISTER SET (MRS) command with BA0=1, BA1=0, BA2=0 
and BA3=0. Bits A0‐A1, A4‐A6 and A10 of this register are initialized with’0’s. 
Figure 24. Mode Register 1 (MR1) Definition
Impedance Autocalibration of Output Buffer and Active Terminator
GDDR5 SGRAMs offer autocalibrating impedance output buffers and on‐die terminations. This enables a 
user to match the driver impedance and terminations to the system within a given range. To adjust the 
impedance, an external precision resistor is connected between the ZQ pin and VSSQ. A nominal resistor 
A1
A0
Driver Strength
00
Auto Calibration On
01
RFU
10
Nominal (60/40)
11
RFU
BA3 BA2 BA1 BA0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
001
0
PLL 
Reset ABI WDBI RDBI PLL
Cal 
Upd
ADR/CMD
Termination
Data 
Termination
Driver 
Strength
A3
A2
Data Termination
00
Disabled
01
ZQ/2
10
ZQ
11
RFU
A5
A4
ADD/CMD Termination
00
CKE# value at Reset
01
ZQ/2
10
ZQ
11
Disabled
A7
PLL
0Off
1On
A11
PLL Reset
0No
1Yes
A9
Write DBI
0On
1Off
A10
ABI
0On
1Off
A8
Read DBI
0On
1Off
A6
Calibration Update
0On
1Off



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