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H5GQ2H24AFR-R0C Datasheet(PDF) 18 Page - Hynix Semiconductor |
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H5GQ2H24AFR-R0C Datasheet(HTML) 18 Page - Hynix Semiconductor |
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18 / 172 page ![]() This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.2 /Nov. 2011 18 H5GQ2H24AFR 2.3. BANK GROUPS For GDDR5 SGRAM devices operating at frequencies above a certain threshold, the activity within a bank group must be restricted to ensure proper operation of the device. The 8 or 16 banks in GDDR5 SGRAMs are divided into four or eight bank groups. The bank groups feature is controlled by bits A10 and A11 in Mode Register 3 (MR3). The assignment of the banks to the bank groups is shown in Table 7. These bank groups allow the specification of different command delay parameters depending on whether back‐to‐back accesses are to banks within one bank group or across bank groups as shown in Table 8. Table 7 Bank Groups Bank Addressing 2G 2G BA3 BA2 BA1 BA0 16 banks 16 banks 00 0 0 0 Group A Group A 10 0 0 1 20 0 1 0 Group B 30 0 1 1 40 1 0 0 Group B Group C 50 1 0 1 60 1 1 0 Group D 70 1 1 1 81 0 0 0 Group C Group E 91 0 0 1 10 1 0 1 0 Group F 11 1 0 1 1 12 1 1 0 0 Group D Group G 13 1 1 0 1 14 1 1 1 0 Group H 15 1 1 1 1 |
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