H5GQ2H24AFR-R0C datasheet(117/172 Pages) HYNIX

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Rev. 1.2 /Nov. 2011

117

H5GQ2H24AFR

5.19. RDQS MODE

For device operation at lower clock frequencies the GDDR5 SGRAM may be set into RDQS mode in which

a READ DATA STROBE (RDQS) in the style of GDDR4 will be sent on the EDC pins along with the READ

data. The controller will use the RDQS to latch the READ data.

RDQS mode is entered by setting the RDQS Mode bit A5 in Mode Register 3 (MR3). When the bit is set, the

GDDR5 SGRAM will asynchronously terminate any EDC hold pattern and drive a logic HIGH after tMRD

at the latest. All features controlled by MR4 are ignored by RDQS mode.

READ commands are executed as in normal mode regarding command to data out delay and pro‐

grammed READ latencies. A fixed clock‐like pattern as shown in Figure 76 is driven on EDC pins in phase

(edge aligned) with the DQ. Prior to the first valid data element, this fixed clock‐like pattern or READ pre‐

amble is driven for 2 tWCK.

No CRC is calculated in RDQS mode, neither for READs nor for WRITEs. The CRC engine is effectively

disabled, and the corresponding WRCRC and RDCRC Mode Register bits are ignored. The PLL may be on

or off with RDQS mode, depending on system considerations and the PLL’s minimum clock frequency.

There is no equivalent WDQS mode; WRITE commands to the GDDR5 SGRAM are not affected by RDQS

mode.

RDQS mode is exited by resetting the RDQS Mode bit. In this case the GDDR5 SGRAM will asynchro‐

nously start driving the EDC hold pattern after tMRD.

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