H5GQ2H24AFR-R0C datasheet(155/172 Pages) HYNIX

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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.2 /Nov. 2011

155

H5GQ2H24AFR

Tables 51, 52 and 53 below provide information for WRITE timings.

Table 51. WCK-to-Data WRITE Timing Sensitivity to VDDQ

Parameter

Symbol

Values

Units

Notes

WCK2DQI Sensitivity to variations in VDDQ for zone_VQ1

PLL on

tI2VQSensZ1

TBD

ps/V

a,b

a. Calculation of tI2VQSensZ1 is performed as follows: 

tI2VQSensZ1 equals the quantity (tWCK2DQI(Zone_VQ1(max)) ‐ tWCK2DQI(Zone_VQ1(min))) 

divided by (VDDQ(Zone_VQ1(max)) ‐ VDDQ(Zone_VQ1(min))) 

= (tWCK2DQI(VDDQ(max)) ‐ tWCK2DQI(VDDQ(min))) / (VDDQ(max) ‐ VDDQ(min)).

b. VDD(typ), Tcase = 85°C, worst‐case process corner.

PLL off

TBD

Table 52. WCK-to-Data WRITE Timing Sensitivity to VDD

Parameter

Symbol

Values

Units

Notes

WCK2DQI Sensitivity to variations in VDD for zone_VD1

PLL on

tI2VDSensZ1

TBD

ps/V

a,b

a. Calculation of tO2VDSensZ1 is performed as follows: 

tI2VDSensZ1 equals the quantity (tWCK2DQI(Zone_VD1(max)) ‐ tWCK2DQI(Zone_VD1(min))) 

divided by (VDD(Zone_VD1(max)) ‐ VDD(Zone_VD1(min))) 

= (tWCK2DQI(VDD(max)) ‐ tWCK2DQI(VDD(min))) / (VDD(max) ‐ VDD(min)).

b. VDDQ(typ), Tcase = 85°C, worst‐case process corner.

PLL off

TBD

Table 53. WCK-to-Data WRITE Timing Sensitivity to Tcase

Parameter

Symbol

Values

Units

Notes

WCK2DQI Sensitivity to variations in Tcase for zone_T1

PLL on

tI2TSensZ1

TBD

ps/°C

a,b

a. Calculation of tI2TSensZ1 is performed as follows: 

tI2TSensZ1 equals the quantity (tWCK2DQI(Zone_T1(max)) ‐ tWCK2DQI(Zone_T1(min))) 

divided by (Tcase(Zone_T1(max)) ‐ Tcase(Zone_T1(min))) 

= (tWCK2DQI(Tcase(max)) ‐ tWCK2DQI(Tcase(min))) / (Tcase(max) ‐ Tcase(min)).

b. VDDQ(typ), VDD(typ), worst‐case process corner.

PLL off

TBD

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