MCP47CMB02 datasheet(111/124 Pages) MICROCHIP

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DS20006089B-page 111

MCP47CXBXX

B.3.1.4

Repeated Start Bit

The Repeated Start bit (see Figure B-5) indicates the

current Master device wishes to continue communicat-

ing with the current Slave device without releasing the

I2C bus. The Repeated Start condition is the same as

the Start condition, except that the Repeated Start bit

follows a Start bit (with the Data bits + A bit) and not a

Stop bit.

The Start bit is the beginning of a data transfer

sequence and is defined as the SDA signal falling when

the SCL signal is “high”.

FIGURE B-5:

Repeated Start Condition

Waveform.

B.3.1.5

Stop Bit

The Stop bit (see Figure B-6) Indicates the end of the

I2C data transfer sequence. The Stop bit is defined as

the SDA signal rising when the SCL signal is “high”.

A Stop bit should reset the I2C interface of the Slave

device.

FIGURE B-6:

Stop Condition Receive or

Transmit Mode.

B.3.2

CLOCK STRETCHING

“Clock Stretching” is something the receiving device

can do, to allow additional time to “respond” to the

“data” that has been received.

B.3.3

ABORTING A TRANSMISSION

If any part of the I2C transmission does not meet the

command format, it is aborted. This can be intentionally

accomplished with a Start or Stop condition. This is done

so that noisy transmissions (usually an extra Start or Stop

condition) are aborted before they corrupt the device.

FIGURE B-7:

Typical 8-Bit I2C Waveform Format.

FIGURE B-8:

I2C Data States and Bit Sequence.

Note 1: A bus collision during the Repeated Start

condition occurs if:

• SDA is sampled low when SCL goes

from low-to-high.

• SCL goes low before SDA is

asserted low. This may indicate that

another Master is attempting to

transmit a data ‘1’.

SDA

SCL

Sr = Repeated Start

1st Bit

SCL

SDA A/A

1st Bit

SDA

SCL

2nd Bit

3rd Bit

4th Bit

5th Bit

6th Bit

7th Bit

8th Bit

A/A

SCL

SDA

Start

Condition

Stop

Condition

Data Allowed

to Change

Data or

A Valid

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