MCP47CMB02 datasheet(112/124 Pages) MICROCHIP

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MCP47CXBXX

DS20006089B-page 112

 2018-2019 Microchip Technology Inc.

B.3.4

SLOPE CONTROL

As the device transitions from High-Speed (HS) mode to

Fats (FS) mode, the slope control parameter will change

from the HS specification to the FS specification.

For FS and HS modes, the device has a spike

suppression and a Schmitt Trigger at SDA and SCL

inputs.

B.3.5

DEVICE ADDRESSING

The I2C Slave address control byte is the first byte

received following the Start condition from the Master

device. This byte has seven bits to specify the Slave

address and the read/write control bit.

Figure B-9 shows the I2C Slave address byte format,

which contains the seven address bits and a

Read/Write (R/W) bit.

FIGURE B-9:

I2C Slave Address Control

Byte.

B.3.6

HS MODE

The I2C specification requires that a High-Speed mode

device must be ‘activated’ to operate in High-Speed

(3.4 Mbit/s) mode. This is done by the Master sending

a special address byte following the Start bit. This byte

is referred to as the High-Speed Master Mode Code

(HSMMC).

The device can now communicate at up to 3.4 Mbit/s

on SDA and SCL lines. The device will switch out of the

HS mode on the next Stop condition.

The Master code is sent as follows:

Start condition (S).

High-Speed Master Mode Code (‘0000 1xxx’);

the ‘xxx’ bits are unique to the HS mode Master.

No Acknowledge (A).

After switching to HS mode, the next transferred byte is

the I2C control byte, which specifies the device to com-

municate with, and any number of data bytes plus

Acknowledgments. The Master device can then either

issue a Repeated Start bit to address a different device

(at high speed) or a Stop bit to return to fast/standard

bus speed. After the Stop bit, any other Master device

(in a Multi-Master system) can arbitrate for the I2C bus.

See Figure B-10 for an illustration of an HS mode

command sequence.

For more information on the HS mode, or other I2C

modes, refer to the “NXP I2C Specification”.

B.3.6.1

Slope Control

The slope control on the SDA output is different

between the Fast/Standard Speed and the High-Speed

Clock modes of the interface.

B.3.6.2

Pulse Gobbler

The pulse gobbler on the SCL pin is automatically

adjusted to suppress spikes <10 ns during HS mode.

FIGURE B-10:

HS Mode Sequence.

Start Bit

Read/Write Bit

Address Byte

R/W ACK

Acknowledge Bit

7-Bit Slave Address

0000 1xxx’b

Slave Address

A/A

Data

S = Start bit

Sr = Repeated Start bit

A = Acknowledge bit

A = Not Acknowledge bit

R/W = Read/Write bit

R/W

P = Stop bit (Stop condition terminates HS mode)

F/S Mode

HS Mode

HS Mode Continues

F/S Mode

Slave Address R/W

HS Select Byte

Control Byte

Command/Data Byte(s)

Control Byte

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