DS20006554A datasheet(23/94 Pages) MICROCHIP

23 / 94 page

ZL30260-ZL30263

Data Sheet

DS20006554A

EEPROM Writes (ZL30261, ZL30263 Only). The internal EEPROM memory is accessible when the EESEL bit is 1.

After driving CSN low, the bus master transmits the write enable command and then drives CSN high to set the

internal write enable latch. The bus master then drives CSN low again and transmits the write command followed by

the 16-bit address followed by the first data byte to be written. The device first copies the page to be written from

EEPROM to its page buffer. The device then receives the first data byte on MOSI, writes it to its page buffer,

increments its internal address register, and prepares to receive the next data byte. If the master continues to

transmit, the device continues to write the data received to its page buffer and continues to increment its address

counter. The address counter rolls over at the 32-byte page boundary (i.e. when the five least-significant address

bits are 11111). When the bus master drives CSN high, the device transfers the data in the page buffer to the

appropriate page in the EEPROM memory. See Figure 7 and Figure 8.

EEPROM Read Status (ZL30261, ZL30263 Only). After the bus master drives CSN high to end an EEPROM write

command, the EEPROM memory is not accessible for up to 5ms while the data is transferred from the page buffer.

To determine when this transfer is complete, the bus master can use the Read Status command. After driving CSN

low, the bus master transmits the Read Status command. The device then responds with the status byte on MISO.

In this byte, the least significant bit is set to 1 if the transfer is still in progress and 0 if the transfer has completed.

Early Termination of Bus Transactions. The bus master can terminate SPI bus transactions at any time by pulling

CSN high. In response to early terminations, the device resets its SPI interface logic and waits for the start of the

next transaction. If a register write transaction is terminated prior to the SCLK edge that latches the least significant

bit of a data byte, the data byte is not written. On devices with internal EEPROM, if an EEPROM write transaction is

terminated prior to the SCLK edge that latches the least significant bit of a data byte, none of the bytes in that write

transaction are written.

Design Option: Wiring MOSI and MISO Together. Because communication between the bus master and the device

is half-duplex, the MOSI and MISO pins can be wired together externally to reduce wire count. To support this option,

the bus master must not drive the MOSI/MISO line when the device is transmitting.

AC Timing. See Table 19 and Figure 18 for AC timing specifications for the SPI interface.

Figure 6 - SPI Read Transaction Functional Timing

Figure 7 - SPI Write Enable Transaction Functional Timing (ZL30261 and ZL30263 Only)

22 23 24 25 26 27 28 29 30 31

SCLK

15 14 13

Command

16-bit Address

Data Byte 1

Data Byte n

MOSI

High Impedance

MISO

SCLK

Command

MOSI

DS20006554A Datasheet(PDF) 23 Page - Microchip Technology

DS20006554A Datasheet(HTML) 23 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94

Datasheet Download

Link URL