DS20006554A datasheet(65/94 Pages) MICROCHIP

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ZL30260-ZL30263

Data Sheet

DS20006554A

F1BP

APLL Fractional Output Divider Truncate Bit Position

14Eh

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

—

FBP[5:0]

Default

Bits 5 to 0: APLL Fractional Output Divider Truncate Bit Position (FBP[5:0]). This unsigned integer specifies

the number of fractional bits that are valid in the fractional output divider value (FDIV). There are 36 fractional bits in

FDIV. The value in this FBP field specifies 36

– number_of_valid_FDIV_fractional_bits. When FBP=0 all 36 FDIV

fractional bits are valid. When FBP=12, the most significant 24 FDIV fractional bits are valid and the least significant

12 bits must be set to 0. This register field is only used when the feedback divider value is expressed in the form

FDIV + FREM / FDEN. FBP values greater than 36 are invalid. See section 5.5.5.

6.3.4

Path 2 Configuration Registers

P2CR1

Path 2 Configuration Register 1

180h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

—

DALIGN

EXTSS[1:0]

—

Default

Bit 6: Align Output Dividers (DALIGN). A 0-to-1 transition on this bit causes a simultaneous reset of the medium-

speed dividers and the low-speed dividers for all output clocks where OCxCR1.PHEN=1. After this reset all PHEN=1

output clocks with frequencies that are exactly integer multiples of one another will be rising-edge aligned as specified

by their OCxPH registers. This bit should be set then cleared once during system startup. Setting this bit during

normal system operation can cause phase jumps in the output clock signals.

Bits 5 to 4: External Switch Source Select (EXTSS[1:0]). This field selects the GPIO source for the external switch

control signal. It is only valid when P2CR3.EXTSW=1. See section 5.5.1.

00 = GPIO0

01 = GPIO1

10 = GPIO2

11 = GPIO3

P2CR3

Path 2 Configuration Register 3

182h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

—

EXTSW

ALTMUX[2:0]

MUX[2:0]

Default

Bit 6: Path 2 External Switching Mode (EXTSW). This bit enables Path 2 external reference switching mode. In

this mode, if the selected GPIO signal is low the Path 2 input mux is controlled by P2CR1.MUX. If the selected GPIO

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