DS20006554A datasheet(80/94 Pages) MICROCHIP

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ZL30260-ZL30263

Data Sheet

DS20006554A

Table 11 - Electrical Characteristics: LVPECL Clock Outputs

VDDOx=VDDH=3.3V±5% or VDDOx=VDDH=2.5V±5% for LVPECL operation.

Characteristics

Symbol

Min.

Typ.

Max.

Units

Notes

Output frequency

fOCD

1045

MHz

Output common-mode voltage,

VDDOx=3.3V

VCM

1.85

1.95

2.05

Note 1. See Figure 16

Output common-Mode voltage,

VDDOx=2.5V

VCM

1.13

1.23

1.33

Note 1. See Figure 16

Output differential voltage

VOD

650

820

1050

Note 1. See Figure 16

Output differential swing, peak-to-peak

VOD

1300

1640

2100

mVPP

Note 1. See Figure 16

Output rise/fall time

tR, tF

150

20%-80%

Output duty cycle

Note 1:

OCxCR2.OCSF=0010, OCxDIFF.VCM=1100, OCxDIFF.VOD=0101. Output must have 100

 DC path between OUTxP and OUTxN

to meet these VOD specs. See Figure 17 parts a) and b) for examples where this DC path is a 100 termination resistor at the

receiver.

Table 12 - Electrical Characteristics: HCSL Clock Outputs

VDDOx=VDDH=3.3V±5% or VDDOx=VDDH=2.5V±5% for HCSL operation.

Characteristics

Symbol

Min.

Typ.

Max.

Units

Notes

Output frequency

fOCHC

250

MHz

Output common-mode voltage

VCM

VOD / 2

Note 1. See Figure 16

Output differential voltage

VOD

0.6

0.75

0.95

Note 1. See Figure 16

Output rise/fall time

tR, tF

250

20%-80%

Output duty cycle

Note 1:

Each of OCxP and OCxN with 50

 termination resistor to ground.

Table 13 - Electrical Characteristics: CMOS and HSTL (Class I) Clock Outputs

Characteristics

Symbol

Min.

Typ.

Max.

Units

Notes

Output frequency

fOCMOS

<<1Hz

250

MHz

Note 1

Output high voltage

VOH

VDDOx

–0.4

VDDOx

Notes 2, 3

Output low voltage

VOL

0.4

Notes 2, 3

Output rise/fall time, VDDOx=1.8V,

OCxCR2.DRIVE=4x

tR, tF

0.4

2pF load

Output rise/fall time, VDDOx=1.8V,

OCxCR2.DRIVE=4x

1.2

15pF load

Output rise/fall time, VDDOx=3.3V,

OCxCR2.DRIVE=1x

0.7

2pF load

Output rise/fall time, VDDOx=3.3V,

OCxCR2.DRIVE=1x

2.2

15pF load

Output duty cycle

Note 4, 6

Output duty cycle

Notes 5, 6

Output duty cycle, OCxNEG single-ended

Output duty cycle, OCxPOS single-ended

Output current when output disabled

IOH

300

A

OCxCR2.OCSF=0

Note 1:

Minimum output frequency is a function of VCO frequency and output divider values and is guaranteed by design.

Note 2:

For HSTL Class I, V

OH and VOL apply for both unterminated loads and for symmetrically terminated loads, i.e. 50 to VDDOx/2.

Note 3:

For VDDOx=3.3V and OCxCR2.DRIVE=1x, IO=4mA. For VDDOx=1.5V and OCxCR2.DRIVE=4x, IO=8mA.

Note 4:

Output clock frequency

≤ 160MHz or VDDOx ≥ 1.8V.

Note 5:

Output clock frequency > 160MHz and VDDOx < 1.8V.

Note 6:

Measured differentially.

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