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DS20006554A Datasheet(PDF) 1 Page - Microchip Technology |
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DS20006554A Datasheet(HTML) 1 Page - Microchip Technology |
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1 / 94 page ![]() ZL30260-ZL30263 1-APLL, 6- or 10-Output Any-to-Any Clock Multiplier and Frequency Synthesizer Data Sheet June 2021 1 DS20006554A Copyright 2021. Microchip Technology Inc. All Rights Reserved. Features • Four Flexible Input Clocks • One crystal/CMOS input • Two differential/CMOS inputs • One single-ended/CMOS input • Any input frequency from 9.72MHz to 1.25GHz (300MHz max for CMOS) • Activity monitors, automatic or manual switching • Glitchless clock switching by pin or register • 6 or 10 Any-Frequency, Any-Format Outputs • Any output frequency from 1Hz to 1045MHz • High-resolution frac-N APLL with 0ppm error • The APLL has a fractional divider and an integer divider to make two independent frequency families • Output jitter from integer multiply and dividers as low as 0.17ps RMS (12kHz-20MHz) • Output jitter from fractional dividers is typically < 1ps RMS, many frequencies <0.5ps RMS • Each output has an independent divider • Each output configurable as LVDS, LVPECL, HCSL, 2xCMOS or HSTL • In 2xCMOS mode, the P and N pins can be different frequencies (e.g. 125MHz and 25MHz) • Multiple output supply voltage banks with CMOS output voltages from 1.5V to 3.3V • Precise output alignment circuitry and per- output phase adjustment • Per-output enable/disable and glitchless start/stop (stop high or low) • General Features • Automatic self-configuration at power-up from external (ZL30260 or 2) or internal (ZL30261 or 3) EEPROM; up to 8 configurations pin-selectable • External feedback for zero-delay applications • Numerically controlled oscillator mode • Spread-spectrum modulation mode • Generates PCIe 1, 2, 3, 4, 5 compliant clocks • Easy-to-configure design requires no external VCXO or loop filter components • SPI or I2C processor Interface • Core supply voltage options: 2.5V only, 3.3V only, 1.8V+2.5V or 1.8V+3.3V • Space-saving 8x8mm QFN56 (0.5mm pitch) Applications • Frequency conversion and frequency synthesis in a wide variety of equipment types Figure 1 - Functional Block Diagram IC1P, IC1N IC2P, IC2N XA XB IC3P xtal driver Frac DIV Int DIV APLL Fractional-N x2 DIV DIV DIV DIV RSTN IF0/CSN SCL/SCLK IF1/MISO SDA/MOSI AC0/GPIO0 Microprocessor Port (SPI or I2C Serial) and GPIO Pins AC1/GPIO1 AC2/GPIO2 TEST/GPIO3 DIV1 DIV2 DIV3 DIV4 DIV5 DIV6 DIV7 DIV8 DIV9 DIV10 OC1P, OC1N OC2P, OC2N VDDOB OC3P, OC3N OC4P, OC4N OC5P, OC5N VDDOC OC6P, OC6N OC7P, OC7N OC8P, OC8N VDDOF OC9P, OC9N VDDOD OC10P, OC10N VDDOA 10-output devices only VDDOE bypass Path 2 x2 Ordering Information ZL30260LDG1 ext. EEPROM 6 Outputs Trays ZL30260LDF1 ext. EEPROM 6 Outputs Tape and Reel ZL30261LDG1 int. EEPROM 6 Outputs Trays ZL30261LDF1 int. EEPROM 6 Outputs Tape and Reel ZL30262LDG1 ext. EEPROM 10 Outputs Trays ZL30262LDF1 ext. EEPROM 10 Outputs Tape and Reel ZL30263LDG1 int. EEPROM 10 Outputs Trays ZL30263LDF1 int. EEPROM 10 Outputs Tape and Reel Matte Tin. Package size: 8 x 8 mm, 56 Pin QFN -40C to +85C Create and sample your own custom ZL30260-3 here: https://clockworks.microchip.com/microchip/design/inputZL Figure 5 Register Map: Section 6.2 |
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