DS20006554A datasheet(83/94 Pages) MICROCHIP

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ZL30260-ZL30263

Data Sheet

DS20006554A

Table 17 - Electrical Characteristics: Clock Buffer (APLL Bypass Path and Path 2)

Characteristics

Min.

Typ.

Max.

Units

Notes

Additive Jitter (Note 7)

100MHz

0.198

ps RMS

Notes 1, 5

125MHz

0.174

156.25MHz

0.155

0.175

200MHz

0.141

400MHz

0.115

800MHz

0.094

Input-to-Output Propagation Delay, from IC1 or IC2 input

2.3

2.6

Note 3

3.4

3.8

Note 4

Input-to-Output Propagation Delay, from IC3 input

1.9

2.3

2.6

Note 3

2.9

3.4

3.8

Note 4

Input-to-Output Propagation Delay, from XA input

2.9

3.3

3.7

Note 3

3.9

4.4

4.9

Note 4

Output-to-Output Skew

100

Note 2

Output Phase Jitter, 50MHz crystal, 50MHz output

0.29

ps RMS

Notes 5, 6

Output Period Jitter, 50MHz crystal, 50MHz output

ps pk-pk

N=10000, Note 6

Output Cycle-to-Cycle Jitter, 50MHz crystal, 50MHz output

ps pk

N=10000, Note 6

Note 1:

APLL bypass enabled, input frequency = output frequency, LVPECL output signal format.

Note 2:

Only applies for outputs that have the same signal format, VDDO voltage, drive strength and load/termination. Also, this skew

spec doesn’t apply to OCxN when an output pair is configured with OCxCR3NEGLSD=1; in this configuration OCxN lags OCxP by

up to 1ns.

Note 3:

Differential outputs with 100

 differential termination (LVDS, LVPECL, Programmable Differential).

Note 4:

CMOS/HSTL outputs, 5pF load.

Note 5:

Jitter calculated from integrated phase noise from 12kHz to 20MHz.

Note 6:

Tested with 50MHz crystal TXC 7M50070021.

Note 7:

Additive jitter contributes in a root-of-sum-of-squares manner. For example, a 156.25MHz input signal with 220fs of jitter will

experience typical additive jitter of 155fs in the device, and the resulting output jitter will be sqrt(2202+1552)=269fs.

Table 18 - Electrical Characteristics: Typical Input-to-Output Clock Delay Through APLL

Mode

Delay, Input Clock Edge to Output Clock Edge

All Modes

Non-deterministic but constant as long as the APLL remains locked

and output clock phases are not adjusted as described in section 5.6.4.

DS20006554A Datasheet(PDF) 83 Page - Microchip Technology

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