DS20006554A datasheet(71/94 Pages) MICROCHIP

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ZL30260-ZL30263

Data Sheet

DS20006554A

OCxDIV1

Output Clock x Divider Register 1

OC1: 205h, OC2: 215h, OC3: 225h, OC4: 235h, OC5: 245h

OC6: 255h, OC7: 265h, OC8: 275h, OC9: 285h, OC10: 295h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

LSDIV[7:0]

Default

Bits 7 to 0: Low-Speed Divider Value (LSDIV[7:0]). The full 25-bit LSDIV[24:0] field spans this register, OCxDIV2,

OCxDIV3. and bit 0 of OCxCR3. LSDIV is an unsigned integer. The frequency of the clock from the medium-speed

divider is divided by LSDIV+1. The OCxCR3.LSSEL and NEGLSD bits control when the output of the low-speed

divider is present on the OCxP and OCxN output pins. OCxCR1.MSDIV must be > 0 for the low-speed divider to

operate. See section 5.6.2.

OCxDIV2

Output Clock x Divider Register 2

OC1: 206h, OC2: 216h, OC3: 226h, OC4: 236h, OC5: 246h

OC6: 256h, OC7: 266h, OC8: 276h, OC9: 286h, OC10: 296h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

LSDIV[15:8]

Default

Bits 7 to 0: Low-Speed Divider Value (LSDIV[15:8]). See the OCxDIV1 register description.

OCxDIV3

Output Clock x Divider Register 3

OC1: 207h, OC2: 217h, OC3: 227h, OC4: 237h, OC5: 247h

OC6: 257h, OC7: 267h, OC8: 277h, OC9: 287h, OC10: 297h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

LSDIV[23:16]

Default

Bits 7 to 0: Low-Speed Divider Value (LSDIV[23:16]). See the OCxDIV1 register description.

OCxDC

Output Clock x Duty Cycle Register

OC1: 208h, OC2: 218h, OC3: 228h, OC4: 238h, OC5: 248h

OC6: 258h, OC7: 268h, OC8: 278h, OC9: 288h, OC10: 298h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

OCDC[7:0]

Default

Bits 7 to 0: Output Clock Duty Cycle (OCDC[7:0]). This field controls the output clock signal duty cycle when

MSDIV>0 and LSDIV>1. When OCDC = 0 the output clock is 50%. Otherwise the clock signal is a pulse with a width

of OCDC number of MSDIV output clock periods. The range of OCDC can create pulse widths from 1 to 255 MSDIV

output clock periods. When OCxCR2.POL=0, the pulse is high and the signal is low the remainder of the cycle. When

POL=1, the pulse is low and the signal is high the remainder of the cycle. See section 5.6.3.

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