DS20006554A datasheet(43/94 Pages) MICROCHIP

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ZL30260-ZL30263

Data Sheet

DS20006554A

CFGSR

Configuration Status Register

40h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

CFGD

—

IF[1:0]

TEST

AC[2:0]

Default

see below

Bit 7: Configured (CFGD). This read-only bit is cleared by assertion of RSTN, MCR1.HRST or MCR1.SRST and

set when any register is written (by auto-configuration or through the processor interface). CFGD=1 indicates that

the device register set is no longer in factory-default state, and, therefore, the device must be reset before a GUI-

generated configuration script is executed.

Bits 5 to 4: Interface Mode (IF[1:0]). These read-only bits are the latched state of the IF1/MISO and IF0/CSN pins

when the RSTN pin transitions high. See section 5.2.

Bit 3: Test Mode (TEST). This read-only bit is the latched state of the TEST/GPIO3 pin when the RSTN pin

transitions high or the MCR1.HRST bit is deasserted. For proper operation it should be 0. See section 5.2.

Bits 2 to 0: Auto-Configuration (AC[2:0]). These bits are the latched state of the AC2/GPIO2, AC1/GPIO1 and

AC0/GPIO0 pins when the RSTN pin transitions high or the MCR1.HRST bit is deasserted. See section 5.2.

GPIOSR

GPIO Status Register

41h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

GPIO3L

GPIO2L

GPIO1L

GPIO0L

GPIO3

GPIO2

GPIO1

GPIO0

Default

pin state

Bit 7: GPIO3 Change Latched Status (GPIO3L). This latched status bit is set to 1 when the GPIO3 status bit

changes state, low-to-high or high-to-low. GPIO3L is cleared when written with a 1. When GPIO3L is set it can cause

an interrupt request if the GPIO3IE interrupt enable bit is set.

Bit 6: GPIO2 Change Latched Status (GPIO2L). This latched status bit is set to 1 when the GPIO2 status bit

changes state, low-to-high or high-to-low. GPIO2L is cleared when written with a 1. When GPIO2L is set it can cause

an interrupt request if the GPIO2IE interrupt enable bit is set.

Bit 5: GPIO1 Change Latched Status (GPIO1L). This latched status bit is set to 1 when the GPIO1 status bit

changes state, low-to-high or high-to-low. GPIO1L is cleared when written with a 1. When GPIO1L is set it can cause

an interrupt request if the GPIO1IE interrupt enable bit is set.

Bit 4: GPIO0 Change Latched Status (GPIO0L). This latched status bit is set to 1 when the GPIO0 status bit

changes state, low-to-high or high-to-low. GPIO0L is cleared when written with a 1. When GPIO0L is set it can cause

an interrupt request if the GPIO0IE interrupt enable bit is set.

Bit 3: GPIO3 State (GPIO3). This real-time status bit indicates the current state of the GPIO3 pin, not influenced by

any inversion that may be specified by GPIOCR2.GPIO3C.

0 = low

1 = high

Bit 2: GPIO2 State (GPIO2). This real-time status bit indicates the current state of the GPIO2 pin, not influenced by

inversion that may be specified by GPIOCR2.GPIO2C.

0 = low

1 = high

DS20006554A Datasheet(PDF) 43 Page - Microchip Technology

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