DS20006554A datasheet(7/94 Pages) MICROCHIP

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ZL30260-ZL30263

Data Sheet

DS20006554A

4. Pin Descriptions

All device inputs and outputs are LVCMOS unless described otherwise. The Type column uses the following symbols:

– input, O – output, A – analog, P – power supply pin. All GPIO and SPI/I2C interface pins have Schmitt-trigger

inputs and have output drivers that can be disabled (high impedance).

Table 1 - Pin Descriptions

Pin #

Name

Type

Description

15, 16

18, 19

IC1P, IC1N

IC2P, IC2N

IC3P

Input Clock Pins

Differential or Single-ended signal format. Programmable frequency.

Differential: See Table 9 for electrical specifications, and see Figure 15 for

recommended external circuitry for interfacing these differential inputs to

LVDS, LVPECL, CML or HSCL output pins on neighboring devices.

Single-ended: For input signal amplitude >2.5V, connect the signal directly to

ICxP pin. For input signal amplitude

≤2.5V, AC-coupling the signal to ICxP

is recommended. Connect the N pin to a capacitor (0.1

F or 0.01F) to

VSS. As shown in Figure 15, the ICxP and ICxN pins are internally biased

to approximately 1.3V. Treat the ICxN pin as a sensitive node; minimize

stubs; do not connect to anything else including other ICxN pins.

Unused: Set ICEN.ICxEN=0. The ICxP and ICxN pins can be left floating.

Note that the IC3N pin is not bonded out. A differential signal can be

connected to IC3P by AC-coupling the POS trace to IC3P and terminating

the signal on the driver side of the coupling cap.

A / I

Crystal or Input Clock Pins

Crystal: MCR2.XAB=01. An on-chip crystal driver circuit is designed to work

with an external crystal connected to the XA and XB pins. See section

5.3.2 for crystal characteristics and recommended external components.

Input Clock: MCR2.XAB=10. An external local oscillator or clock signal can be

connected to the XA pin. The XB pin must be left unconnected. The signal

on XA can be as large as 3.3V even when VDDH is only 2.5V.

8, 9

6, 5

2, 3

55, 56

53, 52

47, 48

45, 44

41, 40

37, 38

35, 34

OC1P, OC1N

OC2P, OC2N

OC3P, OC3N

OC4P, OC4N

OC5P, OC5N

OC6P, OC6N

OC7P, OC7N

OC8P, OC8N

OC9P, OC9N

OC10P, OC10N

Output Clock Pins

LVDS, programmable differential (which includes LVPECL), HCSL, HSTL or

1 or 2 CMOS. Programmable frequency. Programmable VCM and VOD in

programmable differential mode. Programmable drive strength in CMOS

and HSTL modes. See Figure 17 for example external interface circuitry.

See Table 10, Table 11 and Table 12 for electrical specifications for LVDS,

LVPECL and HCSL, respectively.

See Table 13 for electrical specifications for interfacing to CMOS and HSTL

inputs on neighboring devices.

Outputs OC2, OC5, OC7 and OC10 are not present on 6-output products.

RSTN

Reset (Active Low)

When this global asynchronous reset is pulled low, all internal circuitry is reset

to default values. The device is held in reset as long as RSTN is low.

Minimum low time is 1µs.

AC0/GPIO0

AC1/GPIO1

AC2/GPIO2

I/O

Auto-Configure [2:0] / General Purpose I/O 0, 1 and 2

Auto Configure: On the rising edge of RSTN these pins behave as AC[2:0]

and specify one of the configurations stored in ROM or EEPROM. See

section 5.2.

DS20006554A Datasheet(PDF) 7 Page - Microchip Technology

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