DS20006554A datasheet(5/94 Pages) MICROCHIP

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ZL30260-ZL30263

Data Sheet

DS20006554A

1. Application Example

Figure 2 - Application Example: PCIe and Ethernet Clocks for Server Application

2. Detailed Features

2.1

Input Clock Features

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Four input clocks: one crystal/CMOS, two differential/CMOS, one single-ended/CMOS

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Input clocks can be any frequency from 9.72MHz to 1250MHz (differential) or 300MHz (single-ended)

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Supported telecom frequencies include PDH, SDH, Synchronous Ethernet, OTN, wireless

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Activity monitor and glitchless input switching

2.2

APLL Features

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Very high-resolution fractional (i.e. non-integer) frequency multiplication

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Any-to-any frequency conversion with 0ppm error

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Two APLL output dividers: one integer divider (4 to 15 plus half divides 4.5 to 7.5) and one fractional

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Easy-to-configure, completely encapsulated design requires no external VCXO or loop filter

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Bypass mode supports system testing

2.3

Output Clock Features

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Six (ZL30260 or ZL30261) or ten (ZL30262 or ZL30263) low-jitter output clocks

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Each output can be one differential output or two CMOS outputs

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Output clocks can be any frequency from 1Hz to 1045MHz (250MHz max for HCSL, CMOS and HSTL)

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Output jitter from integer multiply and integer dividers as low as 0.17ps RMS (12kHz to 20MHz)

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Output jitter from fractional dividers is typically <1ps RMS, many frequencies <0.5ps RMS (12kHz to

20MHz)

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In CMOS mode, the OCxP and OCxN pins can be different divisors (Example 1: OC3P 125MHz, OC3N

25MHz; Example 2: OC3P 25MHz, OC3N 1Hz/1PPS)

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Outputs directly interface (DC coupled) with LVDS, LVPECL, HSTL, HCSL and CMOS components

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Supported telecom frequencies include PDH, SDH, Synchronous Ethernet, OTN

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Can produce clock frequencies for microprocessors, ASICs, FPGAs and other components

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Can produce PCIe-compliant clocks (PCIe 1, 2, 3, 4 and 5)

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Sophisticated output-to-output phase alignment

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Per-output phase adjustment

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Per-output enable/disable

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Per-output glitchless start/stop (stop high or low)

2.4

General Features

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SPI or I2C serial microprocessor interface

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Automatic self-configuration at power-up; pin control to specify one of 8 stored configurations

ZL30260 and ZL30262: preset configurations in ROM or user configurations in external EEPROM

ZL30261 and ZL30263: user configurations in internal EEPROM

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Numerically controlled oscillator (NCO) mode allows system software to steer DPLL frequency with

resolution better than 0.01ppb (1ppt can be achieved with fractional output divider value >14.56)

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Spread-spectrum modulation mode (meets PCI Express requirements)

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Zero-delay buffer configuration using an external feedback path

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Four general-purpose I/O pins each with many possible status and control options

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Reference can be fundamental-mode crystal, low-cost XO or clock signal from elsewhere in the system

4x 156.25MHz differential

100MHz CMOS

2x 25MHz differential

2x 100MHz differential

25MHz CMOS

ZL30263

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