DS20006554A datasheet(67/94 Pages) MICROCHIP

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ZL30260-ZL30263

Data Sheet

DS20006554A

6.3.5

Output Clock Configuration Registers

OCxCR1

Output Clock x Configuration Register 1

OC1: 200h, OC2: 210h, OC3: 220h, OC4: 230h, OC5: 240h

OC6: 250h, OC7: 260h, OC8: 270h, OC9: 280h, OC10: 290h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

PHEN

MSDIV[6:0]

Default

Bit 7: Phase Alignment Enable (PHEN). This bit enables this output to participate in phase alignment. See section

5.6.5.

0 = Phase alignment disabled for this output

1 = Phase alignment enabled for this output

Bits 6 to 0: Medium-Speed Divider Value (MSDIV[6:0]). This field specifies the setting for the output clock's

medium-speed divider. The divisor is MSDIV+1. Note that if MSDIV is not set to 0 (bypass) then the maximum input

clock frequency to the medium-speed divider is 750MHz and the maximum output clock frequency from the medium-

speed divider is 375MHz. When MSDIV=0, the medium-speed divider, phase adjust, low-speed divider, start/stop

and output duty cycle adjustment circuits are bypassed and the high-frequency clock signal is sent to the directly

output driver. See section 5.6.2.

OCxCR2

Output Clock x Configuration Register 2

OC1: 201h, OC2: 211h, OC3: 221h, OC4: 231h, OC5: 241h

OC6: 251h, OC7: 261h, OC8: 271h, OC9: 281h, OC10: 291h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

—

POL

DRIVE[1:0]

OCSF[3:0]

Default

Bit 6: Clock Path Polarity (POL). The clock path to the output driver is inverted when this bit set. This does not

invert the LSDIV path to the CMOS OCxN pin if that path is enabled. See section 5.6.1.

Bits 5 to 4: CMOS/HSTL Output Drive Strength (DRIVE[1:0]). The CMOS/HSTL output drivers have four equal

sections that can be enabled or disabled to achieve four different drive strengths from 1x to 4x. When the output

power supply VDDOx is 3.3V or 2.5V, the user should start with 1x and only increase drive strength if the output is

highly loaded and signal transition time is unacceptable. When VDDOx is 1.8V or 1.5V the user should start with 4x

and only decrease drive strength if the output signal has unacceptable overshoot. See section 5.6.1.

00 = 1x

01 = 2x

10 = 3x

11 = 4x

Bits 3 to 0: Output Clock Signal Format (OCSF[3:0]). See section 5.6.1.

0000 = Disabled (high-impedance, low power mode)

0001 = LVDS

(VOD is forced to 400mV and OCxDIFF.VOD is ignored)

0010 = Differential (default is LVPECL with VCM=1.2V, programmable using OCxDIFF fields)

0011 = HSTL

(set OCxCR2.DRIVE=11 (4x) to meet JESD8-6)

0100 = Two CMOS: OCxN in phase with OCxP

0101 = One CMOS: OCxP enabled, OCxN high impedance

0110 = One CMOS: OCxP high impedance, OCxN enabled

0111 = Two CMOS: OCxN inverted vs. OCxP

1010 = HCSL

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