DS20006554A datasheet(82/94 Pages) MICROCHIP

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ZL30260-ZL30263

Data Sheet

DS20006554A

Characteristics

Test Conditions

Min

Typ

Max

Units

PCI Express 2.1, Common Refclk Jitter

10kHz to 1.5MHz, Notes 9

0.12

0.3

ps RMS

1.5MHz to 50MHz, Notes 9

1.7

3.1

ps RMS

PCI Express 3.0, Common Refclk Jitter

Note 8

0.09

0.12

ps RMS

PCI Express 4.0, Common Refclk Jitter

Note 8

0.09

0.12

ps RMS

PCI Express 5.0, Common Refclk Jitter

Note 6, 13

0.08

0.09

ps RMS

Period Jitter, 100MHz

Notes 10, 11

9-20

ps pk-pk

Cycle-to-Cycle Jitter, 100MHz

Notes 10, 11

8-18

Random Jitter, fractional output divider

Notes 1, 7

0.26

0.3

ps RMS

Deterministic Jitter, fractional output divider

Note 7

0.3

ps pk-pk

Total Jitter, fractional output divider

12kHz-20MHz

Note 5, 7

3-5

10.25

ps pk-pk

Note 1:

Jitter calculated from integrated phase noise from 12kHz to 20MHz. Phase jitter includes spurs (if present). Random jitter does

not include spurs.

Note 2:

Jitter calculated from integrated phase noise from 1.875MHz to 20MHz.

Note 3:

With 50MHz crystal doubled as APLL input, APLL VCO frequency 3750MHz, divide by 6 using APLL integer divider, then divide

by 4 in output medium-speed divider..

Note 4:

Requires phase alignment capability described in section 5.6.5. Only applies for outputs that have the same signal format, VDDO

voltage. drive strength and loading/termination. Also,

this skew spec doesn’t apply to OCxN when an output pair is configured

with OCxCR3.NEGLSD=1; in this configuration OCxN lags OCxP by up to 1ns.

Note 5:

Total Jitter = Deterministic Jitter + 14 x Random Jitter.

Note 6:

With 50MHz crystal doubled as APLL input. All output clocks 100MHz HCSL format. Jitter is from the PCIe jitter filter combination

that produces the highest jitter.

Note 7:

Output frequencies

 25MHz. Tested at 156.25MHz.

Note 8:

With 50MHz crystal doubled as APLL input. Integer divisor case tested with APLL VCO frequency 3750MHz. Fractional divisor

case tested with VCO frequency 3993.6MHz. PCI Express 3.0 and 4.0 case tested with APLL VCO frequency 3750MHz.

Note 9:

With 50MHz crystal doubled as APLL input and APLL VCO frequency 3993.6MHz. All output clocks 100MHz HCSL format. Jitter

is from the PCIe jitter filter combination that produces the highest jitter. Applies (a) when spread spectrum modulation is disabled

and (b) when spread spectrum modulation in the fractional output divider is 0.25% downspread modulated at 31.5kHz.

Note 10:

Measured using Tektronix MSO71604C, Mixed Signal Oscilloscope with DPOJET software. Measured with 3750MHz VCO

frequency, 200MHz out of the fractional divider, and 100MHz out of the medium-speed divider.

Note 11:

N=10000

Note 12:

AFBDL.FBSEL=11. Tested with 125MHz into IC1, APLL VCO frequency of 3750MHz, APLL integer divider set to 5, OCx medium-

speed dividers set to 6, OCx 125MHz output frequency. Only applies for outputs that have the same signal format, output divider

usage, VDDO voltage, drive strength and load/termination. Also,

this delay spec doesn’t apply to OCxN when an output pair is

configured with OCxCR3.NEGLSD=1; in this configuration OCxN lags OCxP by up to 1ns.

Note 13:

With frequency extended to 200MHz per PCI Express Base 5.0 version 1.0 specification, section 8.6.7 note 2.

Table 16 - Electrical Characteristics: Typical Output Phase Jitter from the APLL Integer Divider

Output Frequency

Output Jitter, ps RMS

125MHz XO Reference1

Output Jitter, ps RMS

50MHz Crystal Reference2

625MHz

0.180

0.185

156.25MHz

0.227

0.23

125MHz

0.228

0.23

25MHz CMOS

0.275

0.29

622.08MHz

0.25

0.26

625MHz * 66/64

0.255

0.26

156.25MHz * 66/64

0.27

0.28

614.4MHz

0.26

0.27

153.6MHz

0.275

0.28

Note 1:

APLL locked to external 125MHz XO (Vectron VCC1-1535-125M000).

Note 2:

APLL locked to external 50MHz crystal (TXC 7M50070021), internal doubler enabled when multiplication is fractional.

Note 3:

All signals are differential unless otherwise stated. Jitter is integrated 12kHz to 5MHz for 25MHz output frequency and 12kHz to

20MHz for all other output frequencies.

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