DS20006554A datasheet(53/94 Pages) MICROCHIP

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ZL30260-ZL30263

Data Sheet

DS20006554A

ACR4

APLL Configuration Register 4

103h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

DECPH

PDSS[2:0]

INCPH

PISS[2:0]

Default

Bit 7: Decrement Phase (DECPH). When PDSS=000, this bit is the APLL phase decrement control signal. See

section 5.5.9.

Bits 6 to 4: Phase Decrement Source Select (PDSS[2:0]). This field specifies the APLL phase decrement control

signal. Every low-to-high transition and every high-to-low transition of the si

gnal decrements the APLL’s output

phase. See section 5.5.9.

000 = DECPH bit

001 = GPIO0

010 = GPIO1

011 = GPIO2

100 = GPIO3

101 to 111 = {unused values}

Bit 3: Increment Phase (INCPH). When PISS=000, this bit is the APLL phase increment control signal. See section

5.5.9.

Bits 2 to 0: Phase Increment Source Select (PISS[2:0]). This field specifies the APLL phase increment control

signal. Every low-to-high transition and every high-to-low transition of the si

gnal increments the APLL’s output phase.

See section 5.5.9.

000 = INCPH bit

001 = GPIO0

010 = GPIO1

011 = GPIO2

100 = GPIO3

101 to 111 = {unused values}

AFBDL

APLL Feedback Divider Write Length

105h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

EXTFB

FBSEL[1:0]

RDCUR

—

AFBDL[2:0]

Default

Bit 7: External Feedback Enable (EXTFB).

0 = Internal feedback through the APLL’s fractional feedback divider

1 = External feedback (typically for output vs. input phase alignment)

Bits 6 to 5: External Feedback Select (FBSEL[1:0]). When EXTFB=1, this field specifies the external feedback

path.

00 = from any OCx output through external path to IC1 input

to APLL’s feedback input

01 = from any OCx output through external path to IC2 input

to APLL’s feedback input

10 = from any OCx output through external path to IC3 input

to APLL’s feedback input

11 = from OC1 output through internal (on-die) path

to APLL’s feedback input

DS20006554A Datasheet(PDF) 53 Page - Microchip Technology

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