DS20006554A datasheet(52/94 Pages) MICROCHIP

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ZL30260-ZL30263

Data Sheet

DS20006554A

ACR2

APLL Configuration Register 2

101h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

—

INTDIV[3:0]

Default

Bits 3 to 0: APLL Integer Divider (INTDIV[3:0]). This field controls the

APLL’s integer divider (see Figure 5). See

section 5.5.4.

0000 = Divide by 4

1000 = Divide by 8

0001 = Divide by 4.5

1001 = Divide by 9

0010 = Divide by 5

1010 = Divide by 10

0011 = Divide by 5.5

1011 = Divide by 11

0100 = Divide by 6 (default)

1100 = Divide by 12

0101 = Divide by 6.5

1101 = Divide by 13

0110 = Divide by 7

1110 = Divide by 14

0111 = Divide by 7.5

1111 = Divide by 15

ACR3

APLL Configuration Register 3

102h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

INMON

EXTSW

ALTMUX[2:0]

APLLMUX[2:0]

Default

Bit 7: APLL Input Monitor Switching Mode (INMON). This bit enables the APLL input monitor loss of signal

reference switching mode. In this mode, if the input specified by the APLLMUX field satisfies the loss-of-signal

condition, the APLL input mux will switch to the input specified by the ALTMUX field. See section 5.5.3.

Bit 6: APLL External Switching Mode (EXTSW). This bit enables APLL external reference switching mode. In this

mode, if the selected GPIO signal is low the APLL input mux is controlled by ACR3.APLLMUX. If the selected GPIO

signal is high the APLL input mux is controlled by ACR3.ALTMUX. ACR1.EXTSS specifies which GPIO pin controls

this behavior. See section 5.5.3.

Bits 5 to 3: APLL Alternate Mux Control (ALTMUX[2:0]). This field specifies the alternate APLL clock source for

external switching (when EXTSW=1) and for automatic switching based on monitor status (when EXTSW=0 an

INMON=1). See section 5.5.3.

000 = IC1 input (default)

001 = IC2 input

010 = IC3 input

011 = XA not doubled

100 = XA doubled (must have MCR2.DBL =1)

101-111 = {reserved values}

Bits 2 to 0: APLL Mux Control (APLLMUX[2:0]). By default this field controls the APLL input mux. It also specifies

the primary APLL clock source for external switching (when EXTSW=1) and for automatic switching based on monitor

status (when EXTSW=0 and INMON=1). See section 5.5.3.

000 = IC1 input

001 = IC2 input

010 = IC3 input

011 = XA not doubled (default)

100 = XA doubled (must have MCR2.DBL =1)

101-111 = {reserved values}

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