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STC12LE5616AD Datasheet(PDF) 31 Page - STCmicro Technology Co,.Ltd |
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STC12LE5616AD Datasheet(HTML) 31 Page - STCmicro Technology Co,.Ltd |
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31 / 377 page  2.1.2 Divider for System Clock A clock divider(CLK_DIV) is designed to slow down the operation speed of STC12C5620AD, to save the operating power dynamically. User can slow down the MCU by means of writing a non-zero value to the CLKS[2:0] bits in the CLK_DIV register. This feature is especially useful to save power consumption in idle mode as long as the user changes the CLKS[2:0] to a non-zero value before entering the idle mode. CLK_DIV register (Clock Divider) SFR Name SFR Address bit B7 B6 B5 B4 B3 B2 B1 B0 CLK_DIV C7H name - - - - - CLKS2 CLKS1 CLKS0 B2-B0 (CLKS2-CLKS0) : 000 External crystal/clock or On-Chip R/C clock is not divided (default state) 001 External crystal/clock or On-Chip R/C clock is divided by 2. 010 External crystal/clock or On-Chip R/C clock is divided by 4. 011 External crystal/clock or On-Chip R/C clock is divided by 8. 100 External crystal/clock or On-Chip R/C clock is divided by 16. 101 External crystal/clock or On-Chip R/C clock is divided by 32. 110 External crystal/clock or On-Chip R/C clock is divided by 64. 111 External crystal/clock or On-Chip R/C clock is divided by 128. Not-divided ÷2 ÷4 ÷8 ÷16 ÷32 ÷64 ÷128 CLKS2,CLKS1,CLKS0 000 001 010 011 100 101 110 111 System Clock (To CPU and peripherals) Clock Structure On-Chip R/C Clock External crystal/clock 31 |
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