STC12LE5616AD datasheet(57/377 Pages) STC

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Chapter 3. Memory Organization

The STC12C5620AD series MCU has separate address space for Program Memory and Data Memory. The

logical separation of program and data memory allows the data memory to be accessed by 8-bit addresses, which

can be quickly stored and manipulated by the CPU.

Program memory (ROM) can only be read, not written to. In the STC12C5620AD series, all the program memory

are on-chip Flash memory, and without the capability of accessing external program memory because of no Ex-

ternal Access Enable (/EA) and Program Store Enable (/PSEN) signals designed.

Data memory occupies a separate address space from program memory. In the 12C5A60S2 series, there are 256

bytes internal scratch-pad RAM and 512 bytes of on-chip expanded RAM(XRAM). The high 128 bytes of 256

bytes internal scrach-pad RAM seemingly overlap with SFRs in address.

Actually, they are distinguished by

different addressing way. Similarly, STC12C5620AD series also have no the capability of accessing external

data memory because of no the bus that access external data memory.

3.1 Program Memory

Program memory is the memory which stores the program codes for the CPU to execute. There is 4/8/12/16/20/2

4/28/30K-bytes of flash memory embedded for program and data storage. The design allows users to configure it

as like there are three individual partition banks inside. They are called AP(application program) region, IAP (In-

Application-Program) region and ISP (In-System-Program) boot region. AP region is the space that user program

is resided. IAP(In-Application-Program) region is the nonvolatile data storage space that may be used to save

important parameters by AP program. In other words, the IAP capability of STC12C5620AD provides the user to

read/write the user-defined on-chip data flash region to save the needing in use of external EEPROM device. ISP

boot region is the space that allows a specific program we calls “ISP program” is resided. Inside the ISP region,

the user can also enable read/write access to a small memory space to store parameters for specific purposes.

Generally, the purpose of ISP program is to fulfill AP program upgrade without the need to remove the device

from system. STC12C5620AD hardware catches the configuration information since power-up duration and

performs out-of-space hardware-protection depending on pre-determined criteria. The criteria is AP region can

be accessed by ISP program only, IAP region can be accessed by ISP program and AP program, and ISP region

is prohibited access from AP program and ISP program itself. But if the “ISP data flash is enabled”, ISP program

can read/write this space. When wrong settings on ISP-IAP SFRs are done, The “out-of-space” happens and

STC12C5620AD follows the criteria above, ignore the trigger command.

After reset, the CPU begins execution from the location 0000H of Program Memory, where should be the starting

of the user’s application code. To service the interrupts, the interrupt service locations (called interrupt vectors)

should be located in the program memory. Each interrupt is assigned a fixed location in the program memory. The

interrupt causes the CPU to jump to that location, where it commences execution of the service routine. External

Interrupt 0, for example, is assigned to location 0003H. If External Interrupt 0 is going to be used, its service

routine must begin at location 0003H. If the interrupt is not going to be used, its service location is available as

general purpose program memory.

The interrupt service locations are spaced at an interval of 8 bytes: 0003H for External Interrupt 0, 000BH for

Timer 0, 0013H for External Interrupt 1, 001BH for Timer 1, etc. If an interrupt service routine is short enough (as

is often the case in control applications), it can reside entirely within that 8-byte interval. Longer service routines

can use a jump instruction to skip over subsequent interrupt locations, if other interrupts are in use.

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