STC12LE5616AD datasheet(70/377 Pages) STC

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PSW register

SFR name Address

bit

PSW

D0H

name

RS1

RS0

CY : Carry flag.

This bit is set when the last arithmetic operation resulted in a carry (addition) or a borrow

(subtrac-tion). It is cleared to logic 0 by all other arithmetic operations.

AC : Auxilliary Carry Flag.(For BCD operations)

This bit is set when the last arithmetic operation resulted in a carry into (addition) or a borrow

from (subtraction) the high order nibble. It is cleared to logic 0 by all other arithmetic operations

F0 : Flag 0.(Available to the user for general purposes)

RS1: Register bank select control bit 1.

RS0: Register bank select control bit 0.

[RS1 RS0] select which register bank is used during register accesses

RS1

RS0

Working Register Bank

(R0~R7) and Address

Bank 0(00H~07H)

Bank 1(08H~0FH)

Bank 2(10H~17H)

Bank 3(18H~1FH)

OV : Overflow flag.

This bit is set to 1 under the following circumstances:

• An ADD, ADDC, or SUBB instruction causes a sign-change overflow.

• A MUL instruction results in an overflow (result is greater than 255).

• A DIV instruction causes a divide-by-zero condition.

The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all other

cases.

F1 : Flag 1. User-defined flag.

: Parity flag.

This bit is set to logic 1 if the sum of the eight bits in the accumulator is odd and cleared if the

sum is even.

STC12LE5616AD Datasheet(PDF) 70 Page - STCmicro Technology Co,.Ltd