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STC12LE5616AD Datasheet(PDF) 48 Page - STCmicro Technology Co,.Ltd |
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STC12LE5616AD Datasheet(HTML) 48 Page - STCmicro Technology Co,.Ltd |
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48 / 377 page ![]() 2.3.3 Power-On Reset (POR) When VCC drops below the detection threshold of POR circuit, all of the logic circuits are reset. When VCC goes back up again, an internal reset is released automatically after a delay of 32768 clocks. The nominal POR detection threshold is around 1.9V for 3V device and 3.3V for 5V device. The Power-On flag, POF/PCON.4, is set by hardware to denote the VCC power has ever been less than the POR voltage. And, it helps users to check if the start of running of the CPU is from power-on or from hardware reset (RST-pin reset), software reset or Watchdog Timer reset. The POF bit should be cleared by software. 2.3.4 MAX810 power-on-Reset delay There is another on-chip POR delay circuit s integrated on STC12C5620AD. This circuit is MAX810—sepcial reset circuit and is controlled by configuring STC-ISP Writter/Programmer shown in the next figure. MAX810 special reset circuit just add 200mS extra reset-delay-time after power-up reset. So it is another power-on reset. 48 |
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