S75WS256NDFBAWMB datasheet(124/216 Pages) SPANSION

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S75WS256Nxx Based MCPs

S75WS-N-00_00_A0 February 17, 2005

Data

Sheet

22 Write Operation Status

The device provides several bits to determine the status of a program or erase operation: DQ1,

DQ2, DQ3, DQ5, DQ6, and DQ7. Table 22.13 and the following subsections describe the function

of these bits. DQ7 and DQ6 each offers a method for determining whether a program or erase

operation is complete or in progress.

22.1 DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase

algorithm is in progress or completed, or whether the device is in Erase Suspend. Data# Polling

is valid after the rising edge of the final WE# pulse in the command sequence. Note that the

Data# Polling is valid only for the last word being programmed in the write-buffer-page

during Write Buffer Programming. Reading Data# Polling status on any word other

than the last word to be programmed in the write-buffer-page will return false status

information.

During the Embedded Program algorithm, the device outputs on DQ7 the complement of the

datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend.

When the Embedded Program algorithm is complete, the device outputs the datum programmed

to DQ7. The system must provide the program address to read valid status information on DQ7.

If a program address falls within a protected sector, Data# Polling on DQ7 is active for approxi-

mately tPSP, then the device returns to the read mode.

During the Embedded Erase algorithm, Data# Polling produces a 0 on DQ7. When the Embedded

Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling pro-

duces a 1 on DQ7. The system must provide an address within any of the sectors selected for

erasure to read valid status information on DQ7.

After an erase command sequence is written, if all sectors selected for erasing are protected,

Data# Polling on DQ7 is active for approximately tASP, then the device returns to the read mode.

If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected

sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7

at an address within a protected sector, the status may not be valid.

Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asyn-

chronously with DQ6–DQ0 while Output Enable (OE#) is asserted low. That is, the device may

change from providing status information to valid data on DQ7. Depending on when the system

samples the DQ7 output, it may read the status or valid data. Even if the device has completed

the program or erase operation and DQ7 has valid data, the data outputs on DQ6-DQ0 may be

still invalid. Valid data on DQ7-D00 will appear on successive read cycles.

Table 22.13 shows the outputs for Data# Polling on DQ7. Figure 22.5 shows the Data# Polling

algorithm. Figure 25.13 in the AC Characteristics section shows the Data# Polling timing diagram.

Notes:

1. VA = Valid adntsbdress for programming. During a sector erase operation, a valid address is any sector address within

the sector being erased. During chip erase, a valid address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = 1 because DQ7 may change simultaneously with DQ5.

Figure 22.5 Data# Polling Algorithm

22.2 DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or

complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read

at any address in the device, and is valid after the rising edge of the final WE# pulse in the com-

mand sequence (prior to the program or erase operation), and during the sector erase time-out.

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